* doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122910 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1e5a199e17836f29b11546ae97b1c03ea9873359..97d34f3c04e0cefe011be0b7d8d3a7f24b01d168 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2007-03-14  Uros Bizjak  <ubizjak@gmail.com>
+
+       * doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option.
+
 2007-03-13  Seongbae Park <seongbae.park@gmail.com>
 
        PR tree-optimization/30590

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d5a5da581041c5d7a92c6fa45fc6713bc7d23222..60122e0a8914b65c8dfde6983e3adb7c5dd6d443 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -10091,11 +10091,12 @@ atomic built-in functions: see @ref{Atomic Builtins} for details.
 
 @item -msahf
 @opindex -msahf
-This option will enable GCC to use SAHF instruction in generated code.  Early
-Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64
-until introduction of Pentium 4 G1 step in December 2005.  LAHF and SAHF are
-load and store instructions, respectively, for certain status flags.  These
-instructions are used for virtualization and floating-point condition handling.
+This option will enable GCC to use SAHF instruction in generated 64-bit code.
+Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported
+by AMD64 until introduction of Pentium 4 G1 step in December 2005.  LAHF and
+SAHF are load and store instructions, respectively, for certain status flags.
+In 64-bit mode, SAHF instruction is used to optimize @code{fmod}, @code{drem}
+or @code{remainder} built-in functions: see @ref{Other Builtins} for details.
 
 @item -mpush-args
 @itemx -mno-push-args