Merge tag 'pull-riscv-to-apply-20251024' of https://github.com/alistair23/qemu into...

Second RISC-V PR for 10.2

* Correct mmu-type property of sifive_u harts in device tree
* Centralize MO_TE uses in a pair of helpers
* Fix Ethernet interface support for microchip-icicle-kit
* Fix mask for smsiaddrcfgh
* Fix env->priv setting in reset_regs_csr()
* Coverity-related fixes
* Fix riscv_cpu_sirq_pending() mask
* Fix a uninitialized variable warning
* Make PMP granularity configurable

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* tag 'pull-riscv-to-apply-20251024' of https://github.com/alistair23/qemu: (25 commits)
  target/riscv: Make PMP CSRs conform to WARL constraints
  target/riscv: Make PMP granularity configurable
  target/riscv: Fix a uninitialized variable warning
  target/riscv: fix riscv_cpu_sirq_pending() mask
  target/riscv/riscv-qmp-cmds.c: coverity-related fixes
  target/riscv/kvm: fix env->priv setting in reset_regs_csr()
  hw/intc: Allow gaps in hartids for aclint and aplic
  aplic: fix mask for smsiaddrcfgh
  microchip icicle: Enable PCS on Cadence Ethernet
  hw/net/cadence_gem: Add pcs-enabled property
  hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
  hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
  target/riscv: Introduce mo_endian_env() helper
  target/riscv: Introduce mo_endian() helper
  target/riscv: Factor MemOp variable out when MO_TE is set
  target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()
  target/riscv: Conceal MO_TE within gen_cmpxchg*()
  target/riscv: Conceal MO_TE within gen_storepair_tl()
  target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()
  target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>