#include <drm/drm_vblank.h>
#include <drm/drm_vblank_work.h>
-#include "i915_drv.h"
-#include "i915_vgpu.h"
#include "i9xx_plane.h"
#include "icl_dsi.h"
#include "intel_atomic.h"
#include "intel_drrs.h"
#include "intel_dsi.h"
#include "intel_fifo_underrun.h"
+#include "intel_parent.h"
#include "intel_pipe_crc.h"
#include "intel_plane.h"
#include "intel_psr.h"
int scanline_end = intel_get_crtc_scanline(crtc);
u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
ktime_t end_vbl_time = ktime_get();
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
local_irq_enable();
- if (intel_vgpu_active(dev_priv))
+ if (intel_parent_vgpu_active(display))
goto out;
if (crtc->debug.start_vbl_count &&
#include "gt/intel_gt_types.h"
#include "i915_drv.h"
-#include "i915_vgpu.h"
#include "i915_vma.h"
#include "i9xx_plane_regs.h"
#include "intel_de.h"
#include "intel_fbc.h"
#include "intel_fbc_regs.h"
#include "intel_frontbuffer.h"
+#include "intel_parent.h"
#define for_each_fbc_id(__display, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
struct intel_plane *plane)
{
struct intel_display *display = to_intel_display(state->base.dev);
- struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
return 0;
}
- if (intel_vgpu_active(i915)) {
+ if (intel_parent_vgpu_active(display)) {
plane_state->no_fbc_reason = "VGPU active";
return 0;
}
{
display->parent->irq->synchronize(display->drm);
}
+
+bool intel_parent_vgpu_active(struct intel_display *display)
+{
+ return display->parent->vgpu_active && display->parent->vgpu_active(display->drm);
+}
bool intel_parent_irq_enabled(struct intel_display *display);
void intel_parent_irq_synchronize(struct intel_display *display);
+bool intel_parent_vgpu_active(struct intel_display *display);
+
#endif /* __INTEL_PARENT_H__ */
"DRM_I915_DEBUG_RUNTIME_PM enabled\n");
}
+static bool vgpu_active(struct drm_device *drm)
+{
+ return intel_vgpu_active(to_i915(drm));
+}
+
static const struct intel_display_parent_interface parent = {
.rpm = &i915_display_rpm_interface,
.irq = &i915_display_irq_interface,
+ .vgpu_active = vgpu_active,
};
const struct intel_display_parent_interface *i915_driver_parent_interface(void)
+++ /dev/null
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef _I915_VGPU_H_
-#define _I915_VGPU_H_
-
-#include <linux/types.h>
-
-struct drm_i915_private;
-
-static inline bool intel_vgpu_active(struct drm_i915_private *i915)
-{
- return false;
-}
-
-#endif /* _I915_VGPU_H_ */
/** @irq: IRQ interface */
const struct intel_display_irq_interface *irq;
+
+ /** @vgpu_active: Is vGPU active? Optional. */
+ bool (*vgpu_active)(struct drm_device *drm);
};
#endif