}
bool g4x_dp_port_enabled(struct intel_display *display,
- i915_reg_t dp_reg, enum port port,
+ intel_reg_t dp_reg, enum port port,
enum pipe *pipe)
{
bool ret;
};
bool g4x_dp_init(struct intel_display *display,
- i915_reg_t output_reg, enum port port)
+ intel_reg_t output_reg, enum port port)
{
const struct intel_bios_encoder_data *devdata;
struct intel_digital_port *dig_port;
#include <linux/types.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
enum pipe;
enum port;
#ifdef I915
const struct dpll *vlv_get_dpll(struct intel_display *display);
bool g4x_dp_port_enabled(struct intel_display *display,
- i915_reg_t dp_reg, enum port port,
+ intel_reg_t dp_reg, enum port port,
enum pipe *pipe);
bool g4x_dp_init(struct intel_display *display,
- i915_reg_t output_reg, enum port port);
+ intel_reg_t output_reg, enum port port);
#else
static inline const struct dpll *vlv_get_dpll(struct intel_display *display)
{
return NULL;
}
static inline bool g4x_dp_port_enabled(struct intel_display *display,
- i915_reg_t dp_reg, int port,
+ intel_reg_t dp_reg, int port,
enum pipe *pipe)
{
return false;
}
static inline bool g4x_dp_init(struct intel_display *display,
- i915_reg_t output_reg, int port)
+ intel_reg_t output_reg, int port)
{
return false;
}
}
bool g4x_hdmi_init(struct intel_display *display,
- i915_reg_t hdmi_reg, enum port port)
+ intel_reg_t hdmi_reg, enum port port)
{
const struct intel_bios_encoder_data *devdata;
struct intel_digital_port *dig_port;
#include <linux/types.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
enum port;
struct drm_atomic_state;
#ifdef I915
bool g4x_hdmi_init(struct intel_display *display,
- i915_reg_t hdmi_reg, enum port port);
+ intel_reg_t hdmi_reg, enum port port);
int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
struct drm_atomic_state *state);
#else
static inline bool g4x_hdmi_init(struct intel_display *display,
- i915_reg_t hdmi_reg, int port)
+ intel_reg_t hdmi_reg, int port)
{
return false;
}
{
struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ intel_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1;
/* FIXME: Move all DSS handling to intel_vdsc.c */
}
struct ibx_audio_regs {
- i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
+ intel_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
};
static void ibx_audio_regs_init(struct intel_display *display,
}
static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
- i915_reg_t reg, u32 val)
+ intel_reg_t reg, u32 val)
{
struct intel_display *display = to_intel_display(crtc_state);
}
static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,
- i915_reg_t reg, u32 val)
+ intel_reg_t reg, u32 val)
{
struct intel_display *display = to_intel_display(crtc_state);
}
static bool check_phy_reg(struct intel_display *display,
- enum phy phy, i915_reg_t reg, u32 mask,
+ enum phy phy, intel_reg_t reg, u32 mask,
u32 expected_val)
{
u32 val = intel_de_read(display, reg);
struct intel_crt {
struct intel_encoder base;
bool force_hotplug_required;
- i915_reg_t adpa_reg;
+ intel_reg_t adpa_reg;
};
static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
}
bool intel_crt_port_enabled(struct intel_display *display,
- i915_reg_t adpa_reg, enum pipe *pipe)
+ intel_reg_t adpa_reg, enum pipe *pipe)
{
u32 val;
{
struct intel_connector *connector;
struct intel_crt *crt;
- i915_reg_t adpa_reg;
+ intel_reg_t adpa_reg;
u8 ddc_pin;
u32 adpa;
#ifndef __INTEL_CRT_H__
#define __INTEL_CRT_H__
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
enum pipe;
struct drm_encoder;
#ifdef I915
bool intel_crt_port_enabled(struct intel_display *display,
- i915_reg_t adpa_reg, enum pipe *pipe);
+ intel_reg_t adpa_reg, enum pipe *pipe);
void intel_crt_init(struct intel_display *display);
void intel_crt_reset(struct drm_encoder *encoder);
#else
static inline bool intel_crt_port_enabled(struct intel_display *display,
- i915_reg_t adpa_reg, enum pipe *pipe)
+ intel_reg_t adpa_reg, enum pipe *pipe)
{
return false;
}
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
+ intel_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
int lane;
intel_de_rmw(display, buf_ctl2_reg,
trans->entries[level].hsw.trans2);
}
-static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
+static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
{
if (DISPLAY_VER(display) >= 14)
return XELPDP_PORT_BUF_CTL1(display, port);
intel_de_posting_read(display, DDI_BUF_CTL(port));
}
-static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
+static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg,
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
{
mutex_lock(&display->dpll.lock);
mutex_unlock(&display->dpll.lock);
}
-static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,
+static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg,
u32 clk_off)
{
mutex_lock(&display->dpll.lock);
mutex_unlock(&display->dpll.lock);
}
-static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
+static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg,
u32 clk_off)
{
return !(intel_de_read(display, reg) & clk_off);
}
static struct intel_dpll *
-_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
+_icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
{
enum intel_dpll_id id;
return crtc_state->cpu_transcoder;
}
-i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
return DP_TP_CTL(encoder->port);
}
-static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 set_bits, wait_bits;
int ret;
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 clr_bits, wait_bits;
int ret;
trans_port_sync_stop_link_train(state, encoder, crtc_state);
}
-static i915_reg_t
+static intel_reg_t
gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)
{
static const enum transcoder trans[] = {
* the bits affect a specific DDI port rather than
* a specific transcoder.
*/
- i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
+ intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
u32 val;
val = intel_de_read(display, reg);
#ifndef __INTEL_DDI_H__
#define __INTEL_DDI_H__
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
struct drm_connector_state;
struct intel_atomic_state;
enum port;
enum transcoder;
-i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
+intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
void intel_ddi_clear_act_sent(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
#include "intel_de.h"
static int __intel_de_wait_for_register(struct intel_display *display,
- i915_reg_t reg, u32 mask, u32 value,
+ intel_reg_t reg, u32 mask, u32 value,
unsigned int timeout_us,
- u32 (*read)(struct intel_display *display, i915_reg_t reg),
+ u32 (*read)(struct intel_display *display, intel_reg_t reg),
u32 *out_val, bool is_atomic)
{
const ktime_t end = ktime_add_us(ktime_get_raw(), timeout_us);
}
static int intel_de_wait_for_register(struct intel_display *display,
- i915_reg_t reg, u32 mask, u32 value,
+ intel_reg_t reg, u32 mask, u32 value,
unsigned int fast_timeout_us,
unsigned int slow_timeout_us,
- u32 (*read)(struct intel_display *display, i915_reg_t reg),
+ u32 (*read)(struct intel_display *display, intel_reg_t reg),
u32 *out_value, bool is_atomic)
{
int ret = -EINVAL;
return ret;
}
-int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_us,
u32 *out_value)
{
return ret;
}
-int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_ms,
u32 *out_value)
{
return ret;
}
-int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_ms,
u32 *out_value)
{
out_value, false);
}
-int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_us,
u32 *out_value)
{
out_value, true);
}
-int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_us)
{
return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
}
-int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_us)
{
return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
}
-int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_ms)
{
return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
}
-int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_ms)
{
return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
}
-u8 intel_de_read8(struct intel_display *display, i915_reg_t reg)
+u8 intel_de_read8(struct intel_display *display, intel_reg_t reg)
{
/* this is only used on VGA registers (possible on pre-g4x) */
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
return intel_uncore_read8(__to_uncore(display), reg);
}
-void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val)
+void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val)
{
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
intel_uncore_write8(__to_uncore(display), reg, val);
}
-u16 intel_de_read16(struct intel_display *display, i915_reg_t reg)
+u16 intel_de_read16(struct intel_display *display, intel_reg_t reg)
{
/* this is only used on MCHBAR registers on pre-SNB */
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 6);
return to_intel_uncore(display->drm);
}
-u8 intel_de_read8(struct intel_display *display, i915_reg_t reg);
-void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val);
-u16 intel_de_read16(struct intel_display *display, i915_reg_t reg);
+u8 intel_de_read8(struct intel_display *display, intel_reg_t reg);
+void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val);
+u16 intel_de_read16(struct intel_display *display, intel_reg_t reg);
static inline u32
-intel_de_read(struct intel_display *display, i915_reg_t reg)
+intel_de_read(struct intel_display *display, intel_reg_t reg)
{
u32 val;
static inline u64
intel_de_read64_2x32_volatile(struct intel_display *display,
- i915_reg_t lower_reg, i915_reg_t upper_reg)
+ intel_reg_t lower_reg, intel_reg_t upper_reg)
{
u64 val;
}
static inline u64
-intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg)
+intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg)
{
- i915_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4);
+ intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4);
u32 lower, upper;
lower = intel_de_read(display, reg);
}
static inline void
-intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
+intel_de_posting_read(struct intel_display *display, intel_reg_t reg)
{
intel_dmc_wl_get(display, reg);
}
static inline void
-intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
+intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val)
{
intel_dmc_wl_get(display, reg);
}
static inline u32
-intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
+intel_de_rmw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
{
u32 val;
return val;
}
-int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_us(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_us,
u32 *out_value);
-int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_ms,
u32 *out_value);
-int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_ms,
u32 *out_value);
-int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg,
u32 mask, u32 value, unsigned int timeout_us,
u32 *out_value);
-int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_us);
-int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_us);
-int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_ms);
-int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
+int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg,
u32 mask, unsigned int timeout_ms);
/*
* a more localised lock guarding all access to that bank of registers.
*/
static inline u32
-intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
+intel_de_read_fw(struct intel_display *display, intel_reg_t reg)
{
u32 val;
}
static inline void
-intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
+intel_de_write_fw(struct intel_display *display, intel_reg_t reg, u32 val)
{
trace_i915_reg_rw(true, reg, val, sizeof(val), true);
intel_uncore_write_fw(__to_uncore(display), reg, val);
}
static inline u32
-intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
+intel_de_rmw_fw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set)
{
u32 old, val;
}
static inline u32
-intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
+intel_de_read_notrace(struct intel_display *display, intel_reg_t reg)
{
return intel_uncore_read_notrace(__to_uncore(display), reg);
}
static inline void
-intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
+intel_de_write_notrace(struct intel_display *display, intel_reg_t reg, u32 val)
{
intel_uncore_write_notrace(__to_uncore(display), reg, val);
}
static __always_inline void
intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
- i915_reg_t reg, u32 val)
+ intel_reg_t reg, u32 val)
{
if (dsb)
intel_dsb_reg_write(dsb, reg, val);
void intel_set_m_n(struct intel_display *display,
const struct intel_link_m_n *m_n,
- i915_reg_t data_m_reg, i915_reg_t data_n_reg,
- i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+ intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+ intel_reg_t link_m_reg, intel_reg_t link_n_reg)
{
intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
intel_de_write(display, data_n_reg, m_n->data_n);
void intel_get_m_n(struct intel_display *display,
struct intel_link_m_n *m_n,
- i915_reg_t data_m_reg, i915_reg_t data_n_reg,
- i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+ intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+ intel_reg_t link_m_reg, intel_reg_t link_n_reg)
{
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
#include <drm/drm_util.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
#include "intel_display_limits.h"
struct drm_atomic_state;
void intel_zero_m_n(struct intel_link_m_n *m_n);
void intel_set_m_n(struct intel_display *display,
const struct intel_link_m_n *m_n,
- i915_reg_t data_m_reg, i915_reg_t data_n_reg,
- i915_reg_t link_m_reg, i915_reg_t link_n_reg);
+ intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+ intel_reg_t link_m_reg, intel_reg_t link_n_reg);
void intel_get_m_n(struct intel_display *display,
struct intel_link_m_n *m_n,
- i915_reg_t data_m_reg, i915_reg_t data_n_reg,
- i915_reg_t link_m_reg, i915_reg_t link_n_reg);
+ intel_reg_t data_m_reg, intel_reg_t data_n_reg,
+ intel_reg_t link_m_reg, intel_reg_t link_n_reg);
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
enum transcoder transcoder);
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
*/
-static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg)
+static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg)
{
u32 val = intel_de_read(display, reg);
void i915_enable_pipestat(struct intel_display *display,
enum pipe pipe, u32 status_mask)
{
- i915_reg_t reg = PIPESTAT(display, pipe);
+ intel_reg_t reg = PIPESTAT(display, pipe);
u32 enable_mask;
drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
void i915_disable_pipestat(struct intel_display *display,
enum pipe pipe, u32 status_mask)
{
- i915_reg_t reg = PIPESTAT(display, pipe);
+ intel_reg_t reg = PIPESTAT(display, pipe);
u32 enable_mask;
drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
}
for_each_pipe(display, pipe) {
- i915_reg_t reg;
+ intel_reg_t reg;
u32 status_mask, enable_mask, iir_bit = 0;
/*
if (iir & GEN8_DE_EDP_PSR) {
struct intel_encoder *encoder;
u32 psr_iir;
- i915_reg_t iir_reg;
+ intel_reg_t iir_reg;
for_each_intel_encoder_with_psr(display->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
static void gen9_dbuf_slice_set(struct intel_display *display,
enum dbuf_slice slice, bool enable)
{
- i915_reg_t reg = DBUF_CTL_S(slice);
+ intel_reg_t reg = DBUF_CTL_S(slice);
bool state;
intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
static void intel_pch_reset_handshake(struct intel_display *display,
bool enable)
{
- i915_reg_t reg;
+ intel_reg_t reg;
u32 reset_bits;
if (DISPLAY_VER(display) >= 35)
}
struct i915_power_well_regs {
- i915_reg_t bios;
- i915_reg_t driver;
- i915_reg_t kvmr;
- i915_reg_t debug;
+ intel_reg_t bios;
+ intel_reg_t driver;
+ intel_reg_t kvmr;
+ intel_reg_t debug;
};
struct i915_power_well_ops {
#include "i915_reg_defs.h"
+typedef i915_reg_t intel_reg_t;
+
#define VLV_DISPLAY_BASE 0x180000
/*
container_of_const((fb), struct intel_framebuffer, base)
struct intel_hdmi {
- i915_reg_t hdmi_reg;
+ intel_reg_t hdmi_reg;
struct {
enum drm_dp_dual_mode_type type;
int max_tmds_clock;
};
struct intel_dp {
- i915_reg_t output_reg;
+ intel_reg_t output_reg;
u32 DP;
int link_rate;
u8 lane_count;
u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
u32 aux_clock_divider);
- i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
- i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
+ intel_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
+ intel_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
/* This is called before a link training is starterd */
void (*prepare_link_retrain)(struct intel_dp *intel_dp,
} dc6_allowed;
struct dmc_fw_info {
u32 mmio_count;
- i915_reg_t mmioaddr[20];
+ intel_reg_t mmioaddr[20];
u32 mmiodata[20];
u32 dmc_offset;
u32 start_mmioaddr;
}
static void disable_event_handler(struct intel_display *display,
- i915_reg_t ctl_reg, i915_reg_t htp_reg)
+ intel_reg_t ctl_reg, intel_reg_t htp_reg)
{
intel_de_write(display, ctl_reg,
REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
}
static bool is_dmc_evt_ctl_reg(struct intel_display *display,
- enum intel_dmc_id dmc_id, i915_reg_t reg)
+ enum intel_dmc_id dmc_id, intel_reg_t reg)
{
u32 offset = i915_mmio_reg_offset(reg);
u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));
}
static bool is_dmc_evt_htp_reg(struct intel_display *display,
- enum intel_dmc_id dmc_id, i915_reg_t reg)
+ enum intel_dmc_id dmc_id, intel_reg_t reg)
{
u32 offset = i915_mmio_reg_offset(reg);
u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));
static bool is_event_handler(struct intel_display *display,
enum intel_dmc_id dmc_id,
unsigned int event_id,
- i915_reg_t reg, u32 data)
+ intel_reg_t reg, u32 data)
{
return is_dmc_evt_ctl_reg(display, dmc_id, reg) &&
REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id;
static bool fixup_dmc_evt(struct intel_display *display,
enum intel_dmc_id dmc_id,
- i915_reg_t reg_ctl, u32 *data_ctl,
- i915_reg_t reg_htp, u32 *data_htp)
+ intel_reg_t reg_ctl, u32 *data_ctl,
+ intel_reg_t reg_htp, u32 *data_htp)
{
if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl))
return false;
static bool disable_dmc_evt(struct intel_display *display,
enum intel_dmc_id dmc_id,
- i915_reg_t reg, u32 data)
+ intel_reg_t reg, u32 data)
{
if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
return false;
dmc_id, expected, found);
for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
- i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
+ intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
found = intel_de_read(display, reg);
expected = dmc_mmiodata(display, dmc, dmc_id, i);
int i;
for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
- i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
+ intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
u32 data = dmc->dmc_info[dmc_id].mmiodata[i];
if (!is_event_handler(display, dmc_id, event_id, reg, data))
struct intel_display *display = m->private;
struct intel_dmc *dmc = display_to_dmc(display);
struct ref_tracker *wakeref;
- i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+ intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
u32 dc6_allowed_count;
if (!HAS_DMC(display))
DMC_VERSION_MINOR(dmc->version));
if (DISPLAY_VER(display) >= 12) {
- i915_reg_t dc3co_reg;
+ intel_reg_t dc3co_reg;
if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
dc3co_reg = DG1_DMC_DEBUG3;
wl->taken = true;
}
-static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
+static bool intel_dmc_wl_reg_in_range(intel_reg_t reg,
const struct intel_dmc_wl_range ranges[])
{
u32 offset = i915_mmio_reg_offset(reg);
}
static bool intel_dmc_wl_check_range(struct intel_display *display,
- i915_reg_t reg,
+ intel_reg_t reg,
u32 dc_state)
{
const struct intel_dmc_wl_range *ranges;
flush_delayed_work(&wl->work);
}
-void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
+void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg)
{
struct intel_dmc_wl *wl = &display->wl;
unsigned long flags;
spin_unlock_irqrestore(&wl->lock, flags);
}
-void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)
+void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg)
{
struct intel_dmc_wl *wl = &display->wl;
unsigned long flags;
#include <linux/workqueue.h>
#include <linux/refcount.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
struct intel_display;
void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state);
void intel_dmc_wl_disable(struct intel_display *display);
void intel_dmc_wl_flush_release_work(struct intel_display *display);
-void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
-void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
+void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg);
+void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg);
void intel_dmc_wl_get_noreg(struct intel_display *display);
void intel_dmc_wl_put_noreg(struct intel_display *display);
const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(encoder);
- i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
+ intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
intel_dp_aux_wait_done(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
- i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
+ intel_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
const unsigned int timeout_ms = 10;
u32 status;
bool done;
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
- i915_reg_t ch_ctl, ch_data[5];
+ intel_reg_t ch_ctl, ch_data[5];
u32 aux_clock_divider;
enum intel_display_power_domain aux_domain;
struct ref_tracker *aux_wakeref;
return ret;
}
-static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
}
}
-static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
+static intel_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
}
}
-static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
+static intel_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
* writes to the group register to write the same value to all the lanes.
*/
static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
- i915_reg_t reg_single,
- i915_reg_t reg_group,
+ intel_reg_t reg_single,
+ intel_reg_t reg_group,
u32 clear, u32 set)
{
u32 old, val;
static bool __printf(6, 7)
__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
- i915_reg_t reg, u32 mask, u32 expected,
+ intel_reg_t reg, u32 mask, u32 expected,
const char *reg_fmt, ...)
{
struct va_format vaf;
{
struct intel_display *display = to_intel_display(encoder);
u32 port_mask;
- i915_reg_t dpll_reg;
+ intel_reg_t dpll_reg;
u32 val;
switch (encoder->port) {
}
}
-static i915_reg_t
+static intel_reg_t
intel_combo_pll_enable_reg(struct intel_display *display,
struct intel_dpll *pll)
{
return ICL_DPLL_ENABLE(pll->info->id);
}
-static i915_reg_t
+static intel_reg_t
intel_tc_pll_enable_reg(struct intel_display *display,
struct intel_dpll *pll)
{
};
struct skl_dpll_regs {
- i915_reg_t ctl, cfgcr1, cfgcr2;
+ intel_reg_t ctl, cfgcr1, cfgcr2;
};
/* this array is indexed by the *shared* pll id */
bool ret = false;
u32 val;
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
+ intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
wakeref = intel_display_power_get_if_enabled(display,
POWER_DOMAIN_DISPLAY_CORE);
static bool icl_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state,
- i915_reg_t enable_reg)
+ intel_reg_t enable_reg)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
+ intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
}
const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
- i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
+ intel_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
if (display->platform.alderlake_s) {
cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
static void icl_pll_power_enable(struct intel_display *display,
struct intel_dpll *pll,
- i915_reg_t enable_reg)
+ intel_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
static void icl_pll_enable(struct intel_display *display,
struct intel_dpll *pll,
- i915_reg_t enable_reg)
+ intel_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
+ intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
+ intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
static void icl_pll_disable(struct intel_display *display,
struct intel_dpll *pll,
- i915_reg_t enable_reg)
+ intel_reg_t enable_reg)
{
/* The first steps are done by intel_ddi_post_disable(). */
static void combo_pll_disable(struct intel_display *display,
struct intel_dpll *pll)
{
- i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
+ intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
icl_pll_disable(display, pll, enable_reg);
}
static void mg_pll_disable(struct intel_display *display,
struct intel_dpll *pll)
{
- i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
+ intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
icl_pll_disable(display, pll, enable_reg);
}
}
static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
- u32 opcode, i915_reg_t reg)
+ u32 opcode, intel_reg_t reg)
{
u32 prev_opcode, prev_reg;
return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
}
-static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
+static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg)
{
return intel_dsb_prev_ins_is_write(dsb,
DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT,
* register.
*/
void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
- i915_reg_t reg, u32 val)
+ intel_reg_t reg, u32 val)
{
/*
* For example the buffer will look like below for 3 dwords for auto
}
void intel_dsb_reg_write(struct intel_dsb *dsb,
- i915_reg_t reg, u32 val)
+ intel_reg_t reg, u32 val)
{
intel_dsb_emit(dsb, val,
(DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
/* Note: mask implemented via byte enables! */
void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
- i915_reg_t reg, u32 mask, u32 val)
+ intel_reg_t reg, u32 mask, u32 val)
{
intel_dsb_emit(dsb, val,
(DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
}
void intel_dsb_poll(struct intel_dsb *dsb,
- i915_reg_t reg, u32 mask, u32 val,
+ intel_reg_t reg, u32 mask, u32 val,
int wait_us, int count)
{
struct intel_crtc *crtc = dsb->crtc;
#include <linux/types.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
struct intel_atomic_state;
struct intel_crtc;
void intel_dsb_cleanup(struct intel_dsb *dsb);
int intel_dsb_exec_time_us(void);
void intel_dsb_reg_write(struct intel_dsb *dsb,
- i915_reg_t reg, u32 val);
+ intel_reg_t reg, u32 val);
void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
- i915_reg_t reg, u32 val);
+ intel_reg_t reg, u32 val);
void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
- i915_reg_t reg, u32 mask, u32 val);
+ intel_reg_t reg, u32 mask, u32 val);
void intel_dsb_noop(struct intel_dsb *dsb, int count);
void intel_dsb_nonpost_start(struct intel_dsb *dsb);
void intel_dsb_nonpost_end(struct intel_dsb *dsb);
void intel_dsb_vblank_evade(struct intel_atomic_state *state,
struct intel_dsb *dsb);
void intel_dsb_poll(struct intel_dsb *dsb,
- i915_reg_t reg, u32 mask, u32 val,
+ intel_reg_t reg, u32 mask, u32 val,
int wait_us, int count);
void intel_dsb_gosub(struct intel_dsb *dsb,
struct intel_dsb *sub_dsb);
#ifndef __INTEL_DVO_DEV_H__
#define __INTEL_DVO_DEV_H__
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
#include "intel_display_limits.h"
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 temp;
/* enable normal train */
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 temp, tries;
/*
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 temp, i, retry;
/*
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 temp, i, j;
ivb_update_fdi_bc_bifurcation(crtc_state);
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 temp;
/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 temp;
/* disable CPU FDI tx and PCH FDI rx */
static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
- i915_reg_t reg = PIPESTAT(display, crtc->pipe);
+ intel_reg_t reg = PIPESTAT(display, crtc->pipe);
u32 enable_mask;
lockdep_assert_held(&display->irq.lock);
enum pipe pipe,
bool enable, bool old)
{
- i915_reg_t reg = PIPESTAT(display, pipe);
+ intel_reg_t reg = PIPESTAT(display, pipe);
lockdep_assert_held(&display->irq.lock);
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
u32 force_bit;
u32 reg0;
- i915_reg_t gpio_reg;
+ intel_reg_t gpio_reg;
struct i2c_algo_bit_data bit_algo;
struct intel_display *display;
};
}
static void
-intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
+intel_gpio_setup(struct intel_gmbus *bus, intel_reg_t gpio_reg)
{
struct i2c_algo_bit_data *algo;
bool enable)
{
struct intel_display *display = to_intel_display(encoder);
- i915_reg_t rekey_reg;
+ intel_reg_t rekey_reg;
u32 rekey_bit = 0;
/* Here we assume HDMI is in TMDS mode of operation */
}
}
-static i915_reg_t
+static intel_reg_t
hsw_dip_data_reg(struct intel_display *display,
enum transcoder cpu_transcoder,
unsigned int type,
struct intel_display *display = to_intel_display(encoder);
const u32 *data = frame;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+ intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
u32 val = intel_de_read(display, reg);
int i;
{
struct intel_display *display = to_intel_display(encoder);
enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
- i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
+ intel_reg_t reg = TVIDEO_DIP_CTL(pipe);
u32 val = intel_de_read(display, reg);
if ((val & VIDEO_DIP_ENABLE) == 0)
struct intel_display *display = to_intel_display(encoder);
const u32 *data = frame;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+ intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
u32 val = intel_de_read(display, reg);
int i;
struct intel_display *display = to_intel_display(encoder);
const u32 *data = frame;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
+ intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
u32 val = intel_de_read(display, reg);
int i;
struct intel_display *display = to_intel_display(encoder);
const u32 *data = frame;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
+ intel_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
int data_size;
int i;
u32 val = intel_de_read(display, ctl_reg);
struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
- i915_reg_t reg = VIDEO_DIP_CTL;
+ intel_reg_t reg = VIDEO_DIP_CTL;
u32 val = intel_de_read(display, reg);
u32 port = VIDEO_DIP_PORT(encoder->port);
{
struct intel_display *display = to_intel_display(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- i915_reg_t reg;
+ intel_reg_t reg;
if ((crtc_state->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- i915_reg_t reg;
+ intel_reg_t reg;
if ((crtc_state->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
- i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+ intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
u32 val = intel_de_read(display, reg);
u32 port = VIDEO_DIP_PORT(encoder->port);
struct intel_display *display = to_intel_display(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
+ intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
u32 val = intel_de_read(display, reg);
assert_hdmi_port_disabled(intel_hdmi);
struct intel_display *display = to_intel_display(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
+ intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
u32 val = intel_de_read(display, reg);
u32 port = VIDEO_DIP_PORT(encoder->port);
const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(encoder);
- i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
+ intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
crtc_state->cpu_transcoder);
u32 val = intel_de_read(display, reg);
const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(encoder);
- i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
+ intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
crtc_state->cpu_transcoder);
u32 val = intel_de_read(display, reg);
static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
int lane, u16 addr, u8 data,
- i915_reg_t mac_reg_addr,
+ intel_reg_t mac_reg_addr,
u8 expected_mac_val)
{
struct intel_display *display = to_intel_display(encoder);
static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
int lane, u16 addr, u8 data,
- i915_reg_t mac_reg_addr,
+ intel_reg_t mac_reg_addr,
u8 expected_mac_val)
{
struct intel_display *display = to_intel_display(encoder);
static void intel_lt_phy_p2p_write(struct intel_encoder *encoder,
u8 lane_mask, u16 addr, u8 data,
- i915_reg_t mac_reg_addr,
+ intel_reg_t mac_reg_addr,
u8 expected_mac_val)
{
int lane;
struct intel_encoder base;
bool is_dual_link;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 a3_power;
struct intel_lvds_pps init_pps;
}
bool intel_lvds_port_enabled(struct intel_display *display,
- i915_reg_t lvds_reg, enum pipe *pipe)
+ intel_reg_t lvds_reg, enum pipe *pipe)
{
u32 val;
struct intel_connector *connector;
const struct drm_edid *drm_edid;
struct intel_encoder *encoder;
- i915_reg_t lvds_reg;
+ intel_reg_t lvds_reg;
u32 lvds;
u8 ddc_pin;
#include <linux/types.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
enum pipe;
struct intel_display;
#ifdef I915
bool intel_lvds_port_enabled(struct intel_display *display,
- i915_reg_t lvds_reg, enum pipe *pipe);
+ intel_reg_t lvds_reg, enum pipe *pipe);
void intel_lvds_init(struct intel_display *display);
struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display);
bool intel_is_dual_link_lvds(struct intel_display *display);
#else
static inline bool intel_lvds_port_enabled(struct intel_display *display,
- i915_reg_t lvds_reg, enum pipe *pipe)
+ intel_reg_t lvds_reg, enum pipe *pipe)
{
return false;
}
return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1;
}
-static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg)
+static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
{
return has_mchbar_mirror(display) &&
in_range32(i915_mmio_reg_offset(reg),
mchbar_mirror_len(display));
}
-static void assert_is_mchbar_reg(struct intel_display *display, i915_reg_t reg)
+static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg)
{
drm_WARN(display->drm, !is_mchbar_reg(display, reg),
"Reading non-MCHBAR register 0x%x\n",
i915_mmio_reg_offset(reg));
}
-u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg)
+u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg)
{
assert_is_mchbar_reg(display, reg);
return intel_de_read16(display, reg);
}
-u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg)
+u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg)
{
assert_is_mchbar_reg(display, reg);
return intel_de_read(display, reg);
}
-u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg)
+u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg)
{
assert_is_mchbar_reg(display, reg);
#include <drm/intel/mchbar_regs.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
struct intel_display;
-u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg);
-u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg);
-u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg);
+u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg);
+u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg);
+u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg);
#endif /* __INTEL_MCHBAR_H__ */
static void assert_pch_dp_disabled(struct intel_display *display,
enum pipe pipe, enum port port,
- i915_reg_t dp_reg)
+ intel_reg_t dp_reg)
{
enum pipe port_pipe;
bool state;
static void assert_pch_hdmi_disabled(struct intel_display *display,
enum pipe pipe, enum port port,
- i915_reg_t hdmi_reg)
+ intel_reg_t hdmi_reg)
{
enum pipe port_pipe;
bool state;
}
static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,
- enum port port, i915_reg_t hdmi_reg)
+ enum port port, intel_reg_t hdmi_reg)
{
u32 val = intel_de_read(display, hdmi_reg);
}
static void ibx_sanitize_pch_dp_port(struct intel_display *display,
- enum port port, i915_reg_t dp_reg)
+ enum port port, intel_reg_t dp_reg)
{
u32 val = intel_de_read(display, dp_reg);
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
+ intel_reg_t reg;
/* FDI relies on the transcoder */
assert_fdi_tx_disabled(display, pipe);
&crtc_state->hw.adjusted_mode;
u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
& TRANSCONF_BPC_MASK) >> 5;
- i915_reg_t reg = TRANS_DP_CTL(pipe);
+ intel_reg_t reg = TRANS_DP_CTL(pipe);
enum port port;
temp = intel_de_read(display, reg);
}
struct pps_registers {
- i915_reg_t pp_ctrl;
- i915_reg_t pp_stat;
- i915_reg_t pp_on;
- i915_reg_t pp_off;
- i915_reg_t pp_div;
+ intel_reg_t pp_ctrl;
+ intel_reg_t pp_stat;
+ intel_reg_t pp_on;
+ intel_reg_t pp_off;
+ intel_reg_t pp_div;
};
static void intel_pps_get_registers(struct intel_dp *intel_dp,
regs->pp_div = PP_DIVISOR(display, pps_idx);
}
-static i915_reg_t
+static intel_reg_t
_pp_ctrl_reg(struct intel_dp *intel_dp)
{
struct pps_registers regs;
return regs.pp_ctrl;
}
-static i915_reg_t
+static intel_reg_t
_pp_stat_reg(struct intel_dp *intel_dp)
{
struct pps_registers regs;
{
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- i915_reg_t pp_stat_reg, pp_ctrl_reg;
+ intel_reg_t pp_stat_reg, pp_ctrl_reg;
int ret;
u32 val;
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
u32 pp;
- i915_reg_t pp_stat_reg, pp_ctrl_reg;
+ intel_reg_t pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
if (!intel_dp_is_edp(intel_dp))
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
u32 pp;
- i915_reg_t pp_stat_reg, pp_ctrl_reg;
+ intel_reg_t pp_stat_reg, pp_ctrl_reg;
lockdep_assert_held(&display->pps.mutex);
{
struct intel_display *display = to_intel_display(intel_dp);
u32 pp;
- i915_reg_t pp_ctrl_reg;
+ intel_reg_t pp_ctrl_reg;
lockdep_assert_held(&display->pps.mutex);
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
u32 pp;
- i915_reg_t pp_ctrl_reg;
+ intel_reg_t pp_ctrl_reg;
lockdep_assert_held(&display->pps.mutex);
wait_backlight_on(intel_dp);
with_intel_pps_lock(intel_dp) {
- i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
pp = ilk_get_pp_control(intel_dp);
return;
with_intel_pps_lock(intel_dp) {
- i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
+ intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
u32 pp;
pp = ilk_get_pp_control(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
- i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
+ intel_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
{
- i915_reg_t pp_reg;
+ intel_reg_t pp_reg;
u32 val;
enum pipe panel_pipe = INVALID_PIPE;
bool locked = true;
EDP_PSR_MASK(intel_dp->psr.transcoder);
}
-static i915_reg_t psr_ctl_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_ctl_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 8)
return EDP_PSR_CTL(display, cpu_transcoder);
return HSW_SRD_CTL;
}
-static i915_reg_t psr_debug_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_debug_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 8)
return EDP_PSR_DEBUG(display, cpu_transcoder);
return HSW_SRD_DEBUG;
}
-static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_perf_cnt_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 8)
return EDP_PSR_PERF_CNT(display, cpu_transcoder);
return HSW_SRD_PERF_CNT;
}
-static i915_reg_t psr_status_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_status_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 8)
return EDP_PSR_STATUS(display, cpu_transcoder);
return HSW_SRD_STATUS;
}
-static i915_reg_t psr_imr_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_imr_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 12)
return TRANS_PSR_IMR(display, cpu_transcoder);
return EDP_PSR_IMR;
}
-static i915_reg_t psr_iir_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_iir_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 12)
return TRANS_PSR_IIR(display, cpu_transcoder);
return EDP_PSR_IIR;
}
-static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,
- enum transcoder cpu_transcoder)
+static intel_reg_t psr_aux_ctl_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder)
{
if (DISPLAY_VER(display) >= 8)
return EDP_PSR_AUX_CTL(display, cpu_transcoder);
return HSW_SRD_AUX_CTL;
}
-static i915_reg_t psr_aux_data_reg(struct intel_display *display,
- enum transcoder cpu_transcoder, int i)
+static intel_reg_t psr_aux_data_reg(struct intel_display *display,
+ enum transcoder cpu_transcoder, int i)
{
if (DISPLAY_VER(display) >= 8)
return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);
{
struct intel_display *display = to_intel_display(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
- i915_reg_t psr_status;
+ intel_reg_t psr_status;
u32 psr_status_mask;
if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
{
struct intel_display *display = to_intel_display(intel_dp);
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 mask;
int err;
struct intel_sdvo_ddc ddc[3];
/* Register for the SDVO device: SDVOB or SDVOC */
- i915_reg_t sdvo_reg;
+ intel_reg_t sdvo_reg;
/*
* Capabilities of the SDVO device returned by
}
bool intel_sdvo_port_enabled(struct intel_display *display,
- i915_reg_t sdvo_reg, enum pipe *pipe)
+ intel_reg_t sdvo_reg, enum pipe *pipe)
{
u32 val;
}
bool intel_sdvo_init(struct intel_display *display,
- i915_reg_t sdvo_reg, enum port port)
+ intel_reg_t sdvo_reg, enum port port)
{
struct intel_encoder *intel_encoder;
struct intel_sdvo *intel_sdvo;
#include <linux/types.h>
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
enum pipe;
enum port;
#ifdef I915
bool intel_sdvo_port_enabled(struct intel_display *display,
- i915_reg_t sdvo_reg, enum pipe *pipe);
+ intel_reg_t sdvo_reg, enum pipe *pipe);
bool intel_sdvo_init(struct intel_display *display,
- i915_reg_t reg, enum port port);
+ intel_reg_t reg, enum port port);
#else
static inline bool intel_sdvo_port_enabled(struct intel_display *display,
- i915_reg_t sdvo_reg, enum pipe *pipe)
+ intel_reg_t sdvo_reg, enum pipe *pipe)
{
return false;
}
static inline bool intel_sdvo_init(struct intel_display *display,
- i915_reg_t reg, enum port port)
+ intel_reg_t reg, enum port port)
{
return false;
}
struct intel_display *display = to_intel_display(encoder);
const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
enum phy phy = intel_encoder_to_phy(encoder);
- i915_reg_t enable_reg = (phy <= PHY_D ?
+ intel_reg_t enable_reg = (phy <= PHY_D ?
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
/*
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
- i915_reg_t enable_reg = (phy <= PHY_D ?
+ intel_reg_t enable_reg = (phy <= PHY_D ?
DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
/*
struct intel_display *display = to_intel_display(tc->dig_port);
enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
enum intel_tc_pin_assignment pin_assignment;
- i915_reg_t reg;
+ intel_reg_t reg;
u32 mask;
u32 val;
{
struct intel_display *display = to_intel_display(tc->dig_port);
enum port port = tc->dig_port->base.port;
- i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+ intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
assert_tc_cold_blocked(tc);
{
struct intel_display *display = to_intel_display(tc->dig_port);
enum port port = tc->dig_port->base.port;
- i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+ intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
u32 val;
assert_tc_cold_blocked(tc);
{
struct intel_display *display = to_intel_display(tc->dig_port);
enum port port = tc->dig_port->base.port;
- i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+ intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
u32 val;
assert_tc_cold_blocked(tc);
{
struct intel_display *display = to_intel_display(tc->dig_port);
enum port port = tc->dig_port->base.port;
- i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
+ intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
assert_tc_cold_blocked(tc);
static bool pipe_scanline_is_moving(struct intel_display *display,
enum pipe pipe)
{
- i915_reg_t reg = PIPEDSL(display, pipe);
+ intel_reg_t reg = PIPEDSL(display, pipe);
u32 line1, line2;
line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
}
static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
- i915_reg_t *dsc_reg, int dsc_reg_num)
+ intel_reg_t *dsc_reg, int dsc_reg_num)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
int pps, u32 pps_val)
{
struct intel_display *display = to_intel_display(crtc_state);
- i915_reg_t dsc_reg[3];
+ intel_reg_t dsc_reg[3];
int i, vdsc_per_pipe, dsc_reg_num;
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
}
-static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+static intel_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
return is_pipe_dsc(crtc, cpu_transcoder) ?
ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
}
-static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
+static intel_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
return is_pipe_dsc(crtc, cpu_transcoder) ?
ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
bool *all_equal)
{
struct intel_display *display = to_intel_display(crtc_state);
- i915_reg_t dsc_reg[3];
+ intel_reg_t dsc_reg[3];
int i, vdsc_per_pipe, dsc_reg_num;
u32 val;
return !(gmch_ctrl & INTEL_GMCH_VGA_DISABLE);
}
-static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
+static intel_reg_t intel_vga_cntrl_reg(struct intel_display *display)
{
if (display->platform.valleyview || display->platform.cherryview)
return VLV_VGACNTRL;
void intel_vga_disable(struct intel_display *display)
{
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
- i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
+ intel_reg_t vga_reg = intel_vga_cntrl_reg(display);
bool mmio = has_vga_mmio_access(display);
bool io_decode;
u8 msr, sr1;
}
static void write_data(struct intel_display *display,
- i915_reg_t reg,
+ intel_reg_t reg,
const u8 *data, u32 len)
{
u32 i, j;
}
static void read_data(struct intel_display *display,
- i915_reg_t reg,
+ intel_reg_t reg,
u8 *data, u32 len)
{
u32 i, j;
struct mipi_dsi_packet packet;
ssize_t ret;
const u8 *header;
- i915_reg_t data_reg, ctrl_reg;
+ intel_reg_t data_reg, ctrl_reg;
u32 data_mask, ctrl_mask;
ret = mipi_dsi_create_packet(&packet, msg);
glk_dsi_disable_mipi_io(encoder);
}
-static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
+static intel_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
{
return display->platform.geminilake || display->platform.broxton ?
BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port);
drm_dbg_kms(display->drm, "\n");
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
- i915_reg_t port_ctrl = display->platform.broxton ?
+ intel_reg_t port_ctrl = display->platform.broxton ?
BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A);
intel_de_write(display, MIPI_DEVICE_READY(display, port),
}
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = port_ctrl_reg(display, port);
+ intel_reg_t port_ctrl = port_ctrl_reg(display, port);
u32 temp;
temp = intel_de_read(display, port_ctrl);
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = port_ctrl_reg(display, port);
+ intel_reg_t port_ctrl = port_ctrl_reg(display, port);
/* de-assert ip_tg_enable signal */
intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0);
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = port_ctrl_reg(display, port);
+ intel_reg_t port_ctrl = port_ctrl_reg(display, port);
bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;
/*
projects / thirdparty / kernel / stable.git / commitdiff
