AVR: Add cost computation for some insn combine patterns.

gcc/
	* config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
	usum_widenqihi and add_zero_extend1.
	[MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
	sub+sign_extend.
	* config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
	Compute exact insn lengths.
	(*usum_widenqihi3): Allow input operands to commute.

diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 1fa4b557f5d8c9c41649fd6066d8bee0b3b6209f..00fce8da15f1242060cb862be5db1e8a4a385df6 100644 (file)
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -12524,10 +12524,25 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
          return true;
        }
 
+      // *usum_widenqihi
+      if (mode == HImode
+         && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+         && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+       {
+         *total = COSTS_N_INSNS (3);
+         return true;
+       }
+
       if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
          && REG_P (XEXP (x, 1)))
        {
-         *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) - 1);
+         *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
+         return true;
+       }
+      if (REG_P (XEXP (x, 0))
+         && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+       {
+         *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
          return true;
        }
 
@@ -12610,6 +12625,29 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
       return true;
 
     case MINUS:
+      // *udiff_widenqihi
+      if (mode == HImode
+         && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+         && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+       {
+         *total = COSTS_N_INSNS (2);
+         return true;
+       }
+      // *sub<mode>3_zero_extend1
+      if (REG_P (XEXP (x, 0))
+         && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+       {
+         *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
+         return true;
+       }
+      // *sub<mode>3.sign_extend2
+      if (REG_P (XEXP (x, 0))
+         && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
+       {
+         *total = COSTS_N_INSNS (2 + GET_MODE_SIZE (mode));
+         return true;
+       }
+
       if (AVR_HAVE_MUL
          && QImode == mode
          && register_operand (XEXP (x, 0), QImode)

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 52b6cff4a8b58d18ce1b3a3dd341b3aca4f14dd7..59ec724f7da740c385e592c915456b126375eb58 100644 (file)
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -1588,12 +1588,10 @@
   ""
   "#"
   "&& reload_completed"
-  [(parallel
-      [(set (match_dup 0)
-            (plus:HI
-              (sign_extend:HI (match_dup 1))
-              (match_dup 2)))
-       (clobber (reg:CC REG_CC))])])
+  [(parallel [(set (match_dup 0)
+                   (plus:HI (sign_extend:HI (match_dup 1))
+                            (match_dup 2)))
+              (clobber (reg:CC REG_CC))])])
 
 
 (define_insn "*addhi3.sign_extend1"
@@ -1607,7 +1605,8 @@
       ? "mov __tmp_reg__,%1\;add %A0,%1\;adc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;dec %B0"
       : "add %A0,%1\;adc %B0,__zero_reg__\;sbrc %1,7\;dec %B0";
   }
-  [(set_attr "length" "5")])
+  [(set (attr "length")
+        (symbol_ref ("4 + reg_overlap_mentioned_p (operands[0], operands[1])")))])
 
 (define_insn_and_split "*addhi3_zero_extend.const_split"
   [(set (match_operand:HI 0 "register_operand"                         "=d")
@@ -1665,7 +1664,7 @@
 
 (define_insn_and_split "*usum_widenqihi3_split"
   [(set (match_operand:HI 0 "register_operand"                          "=r")
-        (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand"  "0"))
+        (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
                  (zero_extend:HI (match_operand:QI 2 "register_operand"  "r"))))]
   ""
   "#"
@@ -1678,7 +1677,7 @@
 
 (define_insn "*usum_widenqihi3"
   [(set (match_operand:HI 0 "register_operand"                          "=r")
-        (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand"  "0"))
+        (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
                  (zero_extend:HI (match_operand:QI 2 "register_operand"  "r"))))
    (clobber (reg:CC REG_CC))]
   "reload_completed"
@@ -2186,7 +2185,8 @@
       ? "mov __tmp_reg__,%2\;sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;inc %B0"
       : "sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc %2,7\;inc %B0";
   }
-  [(set_attr "length" "5")])
+  [(set (attr "length")
+        (symbol_ref ("4 + reg_overlap_mentioned_p (operands[0], operands[2])")))])
 
 ;; "subsi3"
 ;; "subsq3" "subusq3"