KVM: x86: Virtualize AMD CPUID faulting

On AMD CPUs, CPUID faulting support is advertised via
CPUID.80000021H:EAX.CpuidUserDis[bit 17] and enabled by setting
HWCR.CpuidUserDis[bit 35].

Advertise the feature to userspace regardless of host CPU support. Allow
writes to HWCR to set bit 35 when the guest CPUID advertises
CpuidUserDis. Update cpuid_fault_enabled() to check HWCR.CpuidUserDis as
well as MSR_FEATURE_ENABLES.CPUID_GP_ON_CPL_GT_0.

Unlike VMX, SVM prioritizes the CPUID intercept over the #GP induced by
CPUID faulting.[1] This behavior has been confirmed on a Turin CPU (F/M/S
1AH/2/1).

Link: https://lore.kernel.org/r/DS7PR12MB82011943131DF5415365E19E940B2@DS7PR12MB8201.namprd12.prod.outlook.com
Signed-off-by: Jim Mattson <jmattson@google.com>
Link: https://patch.msgid.link/20260527174347.2356165-5-jmattson@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index a14a0f43e04ae8d205f90aefbeb38e2786e8220a..f534f150d1c5966a4d0a1e128310a5c98b6ef391 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -898,6 +898,7 @@
 #define MSR_K7_HWCR_IRPERF_EN_BIT      30
 #define MSR_K7_HWCR_IRPERF_EN          BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
 #define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35
+#define MSR_K7_HWCR_CPUID_USER_DIS     BIT_ULL(MSR_K7_HWCR_CPUID_USER_DIS_BIT)
 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
 #define MSR_K7_HWCR_CPB_DIS_BIT                25

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 1c95d1fa3ead2b8ee9e0e6e8e351e28c69897347..8e5340dd2621189f359b7a6fa755df89df5d4da6 100644 (file)
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1248,7 +1248,7 @@ void kvm_initialize_cpu_caps(void)
                F(AUTOIBRS),
                EMULATED_F(NO_SMM_CTL_MSR),
                /* PrefetchCtlMsr */
-               /* GpOnUserCpuid */
+               EMULATED_F(GP_ON_USER_CPUID),
                /* EPSF */
                F(PREFETCHI),
                F(AVX512_BMM),

diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 95d09ccbf951409e463b7f37831dde81b468b459..fc96ba86c644db64d0d0fd55af8f376614b97039 100644 (file)
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -185,8 +185,9 @@ static inline int guest_cpuid_stepping(struct kvm_vcpu *vcpu)
 
 static inline bool cpuid_fault_enabled(struct kvm_vcpu *vcpu)
 {
-       return vcpu->arch.msr_misc_features_enables &
-                 MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
+       return (vcpu->arch.msr_misc_features_enables &
+               MSR_MISC_FEATURES_ENABLES_CPUID_FAULT) ||
+               (vcpu->arch.msr_hwcr & MSR_K7_HWCR_CPUID_USER_DIS);
 }
 
 static inline bool kvm_is_cpuid_allowed(struct kvm_vcpu *vcpu)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index d8e6877a7a434780c2ea8c781a568165704f7255..57ce0f1f1860b29d79b30d03211e0d46e6735a0d 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -4002,22 +4002,28 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                break;
        case MSR_EFER:
                return set_efer(vcpu, msr_info);
-       case MSR_K7_HWCR:
-               data &= ~(u64)0x40;     /* ignore flush filter disable */
-               data &= ~(u64)0x100;    /* ignore ignne emulation enable */
-               data &= ~(u64)0x8;      /* ignore TLB cache disable */
-
+       case MSR_K7_HWCR: {
                /*
                 * Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2
                 * through at least v6.6 whine if TscFreqSel is clear,
                 * depending on F/M/S.
                 */
-               if (data & ~(BIT_ULL(18) | BIT_ULL(24))) {
+               u64 valid = BIT_ULL(18) | BIT_ULL(24);
+
+               data &= ~(u64)0x40;     /* ignore flush filter disable */
+               data &= ~(u64)0x100;    /* ignore ignne emulation enable */
+               data &= ~(u64)0x8;      /* ignore TLB cache disable */
+
+               if (guest_cpu_cap_has(vcpu, X86_FEATURE_GP_ON_USER_CPUID))
+                       valid |= MSR_K7_HWCR_CPUID_USER_DIS;
+
+               if (data & ~valid) {
                        kvm_pr_unimpl_wrmsr(vcpu, msr, data);
                        return 1;
                }
                vcpu->arch.msr_hwcr = data;
                break;
+       }
        case MSR_FAM10H_MMIO_CONF_BASE:
                if (data != 0) {
                        kvm_pr_unimpl_wrmsr(vcpu, msr, data);