media: ti: j721e-csi2rx: prepare SHIM code for multiple contexts

Currently the SHIM code to configure the context only touches the first
context. Add support for writing to the context's registers based on the
context index.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>

diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
index 23717a3b6c4cf1f702401d16b28393383db195f2..4adfae425f19281ae379186b101ae65198ade9b8 100644 (file)
--- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
+++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
@@ -27,7 +27,7 @@
 #define SHIM_CNTL                      0x10
 #define SHIM_CNTL_PIX_RST              BIT(0)
 
-#define SHIM_DMACNTX                   0x20
+#define SHIM_DMACNTX(i)                        (0x20 + ((i) * 0x20))
 #define SHIM_DMACNTX_EN                        BIT(31)
 #define SHIM_DMACNTX_YUV422            GENMASK(27, 26)
 #define SHIM_DMACNTX_DUAL_PCK_CFG      BIT(24)
@@ -38,7 +38,7 @@
 #define SHIM_DMACNTX_SIZE_16           1
 #define SHIM_DMACNTX_SIZE_32           2
 
-#define SHIM_PSI_CFG0                  0x24
+#define SHIM_PSI_CFG0(i)               (0x24 + ((i) * 0x20))
 #define SHIM_PSI_CFG0_SRC_TAG          GENMASK(15, 0)
 #define SHIM_PSI_CFG0_DST_TAG          GENMASK(31, 16)
 
@@ -568,11 +568,11 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx *ctx)
                break;
        }
 
-       writel(reg, csi->shim + SHIM_DMACNTX);
+       writel(reg, csi->shim + SHIM_DMACNTX(ctx->idx));
 
        reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) |
              FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 0);
-       writel(reg, csi->shim + SHIM_PSI_CFG0);
+       writel(reg, csi->shim + SHIM_PSI_CFG0(ctx->idx));
 }
 
 static void ti_csi2rx_drain_callback(void *param)
@@ -890,7 +890,7 @@ err_dma:
 err_pipeline:
        video_device_pipeline_stop(&ctx->vdev);
        writel(0, csi->shim + SHIM_CNTL);
-       writel(0, csi->shim + SHIM_DMACNTX);
+       writel(0, csi->shim + SHIM_DMACNTX(ctx->idx));
 err:
        ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_QUEUED);
        return ret;
@@ -905,7 +905,7 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue *vq)
        video_device_pipeline_stop(&ctx->vdev);
 
        writel(0, csi->shim + SHIM_CNTL);
-       writel(0, csi->shim + SHIM_DMACNTX);
+       writel(0, csi->shim + SHIM_DMACNTX(ctx->idx));
 
        ret = v4l2_subdev_call(csi->source, video, s_stream, 0);
        if (ret)