x86/CPU/AMD: Add RDSEED fix for Zen5

commit 607b9fb2ce248cc5b633c5949e0153838992c152 upstream.

There's an issue with RDSEED's 16-bit and 32-bit register output
variants on Zen5 which return a random value of 0 "at a rate inconsistent
with randomness while incorrectly signaling success (CF=1)". Search the
web for AMD-SB-7055 for more detail.

Add a fix glue which checks microcode revisions.

  [ bp: Add microcode revisions checking, rewrite. ]

Cc: stable@vger.kernel.org
Signed-off-by: Gregory Price <gourry@gourry.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20251018024010.4112396-1-gourry@gourry.net
[ bp: 6.12 backport: use the alternative microcode version checking. ]
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4810271302d0c93d70873bc1d4cebc94ab971370..437c1db652e9808ff7e2eb9b789d410a1e96e3b2 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1018,8 +1018,43 @@ static void init_amd_zen4(struct cpuinfo_x86 *c)
        }
 }
 
+static bool check_rdseed_microcode(void)
+{
+       struct cpuinfo_x86 *c = &boot_cpu_data;
+       union zen_patch_rev p;
+       u32 min_rev = 0;
+
+       p.ext_fam       = c->x86 - 0xf;
+       p.model         = c->x86_model;
+       p.ext_model     = c->x86_model >> 4;
+       p.stepping      = c->x86_stepping;
+       /* reserved bits are expected to be 0 in test below */
+       p.__reserved    = 0;
+
+       if (cpu_has(c, X86_FEATURE_ZEN5)) {
+               switch (p.ucode_rev >> 8) {
+               case 0xb0021:   min_rev = 0xb00215a; break;
+               case 0xb1010:   min_rev = 0xb101054; break;
+               default:
+                       pr_debug("%s: ucode_rev: 0x%x, current revision: 0x%x\n",
+                                __func__, p.ucode_rev, c->microcode);
+                       return false;
+               }
+       }
+
+       if (!min_rev)
+               return false;
+
+       return c->microcode >= min_rev;
+}
+
 static void init_amd_zen5(struct cpuinfo_x86 *c)
 {
+       if (!check_rdseed_microcode()) {
+               clear_cpu_cap(c, X86_FEATURE_RDSEED);
+               msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+               pr_emerg_once("RDSEED32 is broken. Disabling the corresponding CPUID bit.\n");
+       }
 }
 
 static void init_amd(struct cpuinfo_x86 *c)