crypto: qat - add get_svc_slice_cnt() in device data structure

Enhance the adf_hw_device_data structure by introducing a new callback
function get_svc_slice_cnt(), which provides a mechanism to query the
total number of accelerator available on the device for a specific
service.

Implement adf_gen4_get_svc_slice_cnt() for QAT GEN4 devices to support this
new interface. This function returns the total accelerator count for a
specific service.

Co-developed-by: George Abraham P <george.abraham.p@intel.com>
Signed-off-by: George Abraham P <george.abraham.p@intel.com>
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
index 67a1c1d8e23ea2db31180f6e39579bc9224f4b0b..53fa91d577ed084078d7b8c9148bc44c15e59b18 100644 (file)
--- a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
@@ -468,6 +468,7 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
        hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
        hw_data->clock_frequency = ADF_420XX_AE_FREQ;
        hw_data->services_supported = adf_gen4_services_supported;
+       hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt;
 
        adf_gen4_set_err_mask(&hw_data->dev_err_mask);
        adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
index 9b728dba048b56f6de7972d2114c096677cd3796..740f68a36ac517abb70096ff10220494d436d595 100644 (file)
--- a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -462,6 +462,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
        hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
        hw_data->clock_frequency = ADF_4XXX_AE_FREQ;
        hw_data->services_supported = adf_gen4_services_supported;
+       hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt;
 
        adf_gen4_set_err_mask(&hw_data->dev_err_mask);
        adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
index f76e0f6c66aed46f1a6955e264162f9a89c4e021..9fe3239f01143bf8552f8e9c1a6adc67261cf315 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
@@ -319,6 +319,8 @@ struct adf_hw_device_data {
        u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
        int (*dev_config)(struct adf_accel_dev *accel_dev);
        bool (*services_supported)(unsigned long mask);
+       u32 (*get_svc_slice_cnt)(struct adf_accel_dev *accel_dev,
+                                enum adf_base_services svc);
        struct adf_pfvf_ops pfvf_ops;
        struct adf_hw_csr_ops csr_ops;
        struct adf_dc_ops dc_ops;

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
index 5e4b45c3fabefe52471ec2948a20c617143cbe79..349fdb323763c869812a8e0d5cf21c5dddd3fd70 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
@@ -580,3 +580,21 @@ void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data)
        device_data->svc_ae_mask[SVC_DECOMP] = 0;
 }
 EXPORT_SYMBOL_GPL(adf_gen4_init_num_svc_aes);
+
+u32 adf_gen4_get_svc_slice_cnt(struct adf_accel_dev *accel_dev,
+                              enum adf_base_services svc)
+{
+       struct adf_rl_hw_data *device_data = &accel_dev->hw_device->rl_data;
+
+       switch (svc) {
+       case SVC_SYM:
+               return device_data->slices.cph_cnt;
+       case SVC_ASYM:
+               return device_data->slices.pke_cnt;
+       case SVC_DC:
+               return device_data->slices.dcpr_cnt;
+       default:
+               return 0;
+       }
+}
+EXPORT_SYMBOL_GPL(adf_gen4_get_svc_slice_cnt);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
index 7fa203071c012752790432acdb0762156ad41dc4..cd26b6724c430a48f5e0d302eea1ff63837a9916 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
@@ -176,5 +176,7 @@ void adf_gen4_bank_drain_finish(struct adf_accel_dev *accel_dev,
 bool adf_gen4_services_supported(unsigned long service_mask);
 void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
 void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data);
+u32 adf_gen4_get_svc_slice_cnt(struct adf_accel_dev *accel_dev,
+                              enum adf_base_services svc);
 
 #endif

diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.c b/drivers/crypto/intel/qat/qat_common/adf_rl.c
index 77465ab6702c3c10b1f20940266c1bc266739028..c6a54e465931620b554cfd5bfdeab25529fd0364 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_rl.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_rl.c
@@ -529,21 +529,9 @@ u32 adf_rl_calculate_slice_tokens(struct adf_accel_dev *accel_dev, u32 sla_val,
        if (!sla_val)
                return 0;
 
+       /* Handle generation specific slice count adjustment */
        avail_slice_cycles = hw_data->clock_frequency;
-
-       switch (svc_type) {
-       case SVC_ASYM:
-               avail_slice_cycles *= device_data->slices.pke_cnt;
-               break;
-       case SVC_SYM:
-               avail_slice_cycles *= device_data->slices.cph_cnt;
-               break;
-       case SVC_DC:
-               avail_slice_cycles *= device_data->slices.dcpr_cnt;
-               break;
-       default:
-               break;
-       }
+       avail_slice_cycles *= hw_data->get_svc_slice_cnt(accel_dev, svc_type);
 
        do_div(avail_slice_cycles, device_data->scan_interval);
        allocated_tokens = avail_slice_cycles * sla_val;