RISC-V: Add test for vec_duplicate + vmsltu.vv combine with GR2VR cost 0, 1 and 15

Add asm dump check and run test for vec_duplicate + vmsltu.vv
combine to vmsltu.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vmsltu.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index f3975be915b234c4eb1afb6dd2b1c6b6bd3d9a70..7e3ad1f70fc01e27cc92143725e92de585efecd8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 7d3e2af2ddd7b11bc16fbd3829a8fb957af62c91..cce222672c4518de1a7e0375dd44a39790099371 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index a581c027e039a4a3b9c38daedb2e0e5669c81f2c..664d88da4e875d415a088f3e4d9a1a9c7649a8d3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -41,3 +41,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vwmaccu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 65e98066b8e411939040239fafa05b92ddf373c0..fd5ed561730852ee1b937012f1e534a1e84a54ed 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -28,3 +28,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index f2beb3b2f119cf8c91327da70d9d553bffa6ae9d..d3cdc4ab239f672b602b0d26fe5b211fb7b79f79 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 949210964f6098e260ac14c304f5c6430f71f7fa..10f5bf09b43124267355bdbb747bc04bcc5b7d26 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 01027351b48b56c20acaa232e544e6f0a505b798..a7c888848f6333f53716ce18eb29e8c4769c1a58 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 5f0d75b5a97ce01ab8767ce324f6106425de24aa..55c2a967611bad5fdb6cc95a109315e51d7e2fbf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -28,3 +28,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 8ac64b6a865050e305afcd0b8924c0c359bdce40..233613df1b3df67880363c8f909f5e8761ccde22 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index cc126c2742707b11a635d6f3cc78a51ab90a256c..ac68d6e9ebbf9d0d8b0448d1eaaff3d6cbcd7bd0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 7642add8073d2f13b602dd914bc2bd5adc106ffb..bfdf5c1512416cba1b1f35405053ab511e522bd6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -38,3 +38,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index c5f973024100471f3d86d772e796b9c33a2f9e6c..d6e64ef6f923d4c286546cff52e42f30abfe48dc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -28,3 +28,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vmseq.vx} } } */
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
+/* { dg-final { scan-assembler-not {vmsltu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 4a30de478650545a5a47a2c26e61a9d768a70f6c..764f301d0820a1ccf3df1f539a7b5c6e2ecb656a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -424,6 +424,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
   DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne)                            \
+  DEF_VX_BINARY_CASE_0_WRAP(T, <, ltu)                            \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)           \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 45976f7c4f4ac12db9448ba3a9fc92ac6fa0e98a..d4834c794148b9d65571018afdfe4fc4f4480dba 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -6430,4 +6430,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, ne)[][3][N] =
   },
 };
 
+uint8_t TEST_BINARY_DATA(uint8_t, ltu)[][3][N] =
+{
+  {
+    { 127 },
+    {
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+      127, 127, 127, 127,
+      128, 128, 128, 128,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+    },
+  },
+  {
+    { 255 },
+    {
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         2,   2,   2,   2,
+       255, 255, 255, 255,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, ltu)[][3][N] =
+{
+  {
+    { 32767 },
+    {
+          0,     0,     0,     0,
+          1,     1,     1,     1,
+      32767, 32767, 32767, 32767,
+      32768, 32768, 32768, 32768,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+    },
+  },
+  {
+    { 65535 },
+    {
+           0,     0,     0,     0,
+           1,     1,     1,     1,
+           2,     2,     2,     2,
+       65535, 65535, 65535, 65535,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, ltu)[][3][N] =
+{
+  {
+    { 2147483647 },
+    {
+               0,          0,          0,          0,
+               1,          1,          1,          1,
+      2147483647, 2147483647, 2147483647, 2147483647,
+      2147483648, 2147483648, 2147483648, 2147483648,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+    },
+  },
+  {
+    { 4294967295 },
+    {
+                0,          0,          0,          0,
+                1,          1,          1,          1,
+                2,          2,          2,          2,
+       4294967295, 4294967295, 4294967295, 4294967295,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, ltu)[][3][N] =
+{
+  {
+    { 9223372036854775807ull },
+    {
+                           0,                      0,                      0,                      0,
+                           1,                      1,                      1,                      1,
+      9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
+      9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
+    },
+    {
+        1,   1,   1,   1,
+        1,   1,   1,   1,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+    },
+  },
+  {
+    { 18446744073709551615ull },
+    {
+                             0,                       0,                       0,                       0,
+                             1,                       1,                       1,                       1,
+                             2,                       2,                       2,                       2,
+       18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+    },
+    {
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         1,   1,   1,   1,
+         0,   0,   0,   0,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u16.c
new file mode 100644 (file)
index 0000000..38283c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME ltu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u32.c
new file mode 100644 (file)
index 0000000..dadb399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint32_t
+#define NAME ltu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u64.c
new file mode 100644 (file)
index 0000000..1b961c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME ltu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u8.c
new file mode 100644 (file)
index 0000000..316df98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsltu-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME ltu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"