]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
misc: microchip: pci1xxxx: Fix incorrect IRQ status handling during ack
authorRengarajan S <rengarajan.s@microchip.com>
Thu, 13 Mar 2025 17:08:56 +0000 (22:38 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 15 Apr 2025 14:22:19 +0000 (16:22 +0200)
Under irq_ack, pci1xxxx_assign_bit reads the current interrupt status,
modifies and writes the entire value back. Since, the IRQ status bit
gets cleared on writing back, the better approach is to directly write
the bitmask to the register in order to preserve the value.

Fixes: 1f4d8ae231f4 ("misc: microchip: pci1xxxx: Add gpio irq handler and irq helper functions irq_ack, irq_mask, irq_unmask and irq_set_type of irq_chip.")
Cc: stable <stable@kernel.org>
Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
Link: https://lore.kernel.org/r/20250313170856.20868-3-rengarajan.s@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

index 21255cdb24c1eb3d3f865202e5d390e96cebc968..98d3d123004c887bb8e28655a5558a102935f1fc 100644 (file)
@@ -168,7 +168,7 @@ static void pci1xxxx_gpio_irq_ack(struct irq_data *data)
        unsigned long flags;
 
        spin_lock_irqsave(&priv->lock, flags);
-       pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true);
+       writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio));
        spin_unlock_irqrestore(&priv->lock, flags);
 }