phy: qcom: pcie: Determine has_nocsr_reset dynamically

Decide the in-driver logic based on whether the nocsr reset is present
and defer checking the appropriateness of that to dt-bindings to save
on boilerplate.

Reset controller APIs are fine consuming a nullptr, so no additional
checks are necessary there.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Link: https://lore.kernel.org/r/20250411113120.651363-2-quic_wenbyao@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index c232b8fe9846a52e4a7cbca538c1dc7c6c148c86..3fd911506f08d92cc9cfee03d4cb8efbe4280fdb 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -3021,8 +3021,6 @@ struct qmp_phy_cfg {
 
        bool skip_start_delay;
 
-       bool has_nocsr_reset;
-
        /* QMP PHY pipe clock interface rate */
        unsigned long pipe_clock_rate;
 
@@ -4020,7 +4018,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
        .phy_status             = PHYSTATUS_4_20,
-       .has_nocsr_reset        = true,
 
        /* 20MHz PHY AUX Clock */
        .aux_clock_rate         = 20000000,
@@ -4053,7 +4050,6 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
        .phy_status             = PHYSTATUS_4_20,
-       .has_nocsr_reset        = true,
 
        /* 20MHz PHY AUX Clock */
        .aux_clock_rate         = 20000000,
@@ -4173,7 +4169,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
        .phy_status             = PHYSTATUS_4_20,
-       .has_nocsr_reset        = true,
 };
 
 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
@@ -4207,7 +4202,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
        .phy_status             = PHYSTATUS_4_20,
-       .has_nocsr_reset        = true,
 };
 
 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
@@ -4239,7 +4233,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
 
        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
        .phy_status             = PHYSTATUS_4_20,
-       .has_nocsr_reset        = true,
 };
 
 static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
@@ -4557,12 +4550,10 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
        if (ret)
                return dev_err_probe(dev, ret, "failed to get resets\n");
 
-       if (cfg->has_nocsr_reset) {
-               qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
-               if (IS_ERR(qmp->nocsr_reset))
-                       return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
-                                               "failed to get no-csr reset\n");
-       }
+       qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");
+       if (IS_ERR(qmp->nocsr_reset))
+               return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
+                                                       "failed to get no-csr reset\n");
 
        return 0;
 }