arm64: zynqmp: Disable coresight by default

[ Upstream commit 0e3f9140ad04dca9a6a93dd6a6decdc53fd665ca ]

When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index b1b31dcf6291b057087c097dfd147360c5930fdd..e2ad5fb2cb0a4e5152884b4cfddbd47bce8881d5 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -450,6 +450,7 @@
                        reg = <0x0 0xfec10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu0>;
+                       status = "disabled";
                };
 
                cpu1_debug: debug@fed10000 {
@@ -457,6 +458,7 @@
                        reg = <0x0 0xfed10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu1>;
+                       status = "disabled";
                };
 
                cpu2_debug: debug@fee10000 {
@@ -464,6 +466,7 @@
                        reg = <0x0 0xfee10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu2>;
+                       status = "disabled";
                };
 
                cpu3_debug: debug@fef10000 {
@@ -471,6 +474,7 @@
                        reg = <0x0 0xfef10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu3>;
+                       status = "disabled";
                };
 
                /* GDMA */