]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tue, 10 Dec 2024 23:06:15 +0000 (01:06 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 11 Feb 2025 09:20:31 +0000 (10:20 +0100)
In preparation to enable the second HDMI output port found on RK3588
SoC, add the related PHY node.  This requires a GRF, hence add the
dependent node as well.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi

index 505cdd7b518ed687865deebcad553fe92b111fd8..f5ffe593a1826b180f8144b1b688223fc95168d5 100644 (file)
                };
        };
 
+       hdptxphy1_grf: syscon@fd5e4000 {
+               compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+               reg = <0x0 0xfd5e4000 0x0 0x100>;
+       };
+
        spdif_tx5: spdif-tx@fddb8000 {
                compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
                reg = <0x0 0xfddb8000 0x0 0x1000>;
                };
        };
 
+       hdptxphy1: phy@fed70000 {
+               compatible = "rockchip,rk3588-hdptx-phy";
+               reg = <0x0 0xfed70000 0x0 0x2000>;
+               clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+               clock-names = "ref", "apb";
+               #phy-cells = <0>;
+               resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
+                        <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
+                        <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
+                        <&cru SRST_HDPTX1_LCPLL>;
+               reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+                             "lcpll";
+               rockchip,grf = <&hdptxphy1_grf>;
+               status = "disabled";
+       };
+
        usbdp_phy1: phy@fed90000 {
                compatible = "rockchip,rk3588-usbdp-phy";
                reg = <0x0 0xfed90000 0x0 0x10000>;