]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/i915: switch i915 core to generic VLV IOSF SB functions
authorJani Nikula <jani.nikula@intel.com>
Mon, 12 May 2025 14:56:55 +0000 (17:56 +0300)
committerJani Nikula <jani.nikula@intel.com>
Tue, 13 May 2025 07:26:45 +0000 (10:26 +0300)
We'll want to relocate the unit specific functions to display, making
them inaccessible to i915 core. As there aren't that many users in i915
core, we can just convert them to the generic VLV IOSF SB read/write
functions.

v2: Use BIT(unit) for get/put

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/3162c8768eeeba928bbc3d4aa2ddfc6a1030a451.1747061743.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
drivers/gpu/drm/i915/gt/intel_rps.c
drivers/gpu/drm/i915/soc/intel_dram.c

index 0704fe763afed67f62dbe7922b755bc1bef2b845..a059c6488b3dbf5fbb5ce038ef634dc1a0b970ea 100644 (file)
@@ -366,9 +366,9 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
                drm_printf(p, "SW control enabled: %s\n",
                           str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
 
-               vlv_punit_get(i915);
-               freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
-               vlv_punit_put(i915);
+               vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
+               freq_sts = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
+               vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
 
                drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 
index 7fa341d2bfe4fbd3db303503d3dbf2b09ef32dbb..37487d2f121dcf93f58d709b8a226de69d2325db 100644 (file)
@@ -820,9 +820,9 @@ static int vlv_rps_set(struct intel_rps *rps, u8 val)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        int err;
 
-       vlv_punit_get(i915);
-       err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val);
-       vlv_punit_put(i915);
+       vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
+       err = vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_REQ, val);
+       vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
 
        GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
                 val, intel_gpu_freq(rps, val));
@@ -1268,7 +1268,7 @@ static int chv_rps_max_freq(struct intel_rps *rps)
        struct intel_gt *gt = rps_to_gt(rps);
        u32 val;
 
-       val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE);
 
        switch (gt->info.sseu.eu_total) {
        case 8:
@@ -1295,7 +1295,7 @@ static int chv_rps_rpe_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val;
 
-       val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_GPU_DUTYCYCLE_REG);
        val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT;
 
        return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
@@ -1306,7 +1306,7 @@ static int chv_rps_guar_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val;
 
-       val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE);
 
        return val & FB_GFX_FREQ_FUSE_MASK;
 }
@@ -1316,7 +1316,7 @@ static u32 chv_rps_min_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val;
 
-       val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, FB_GFX_FMIN_AT_VMIN_FUSE);
        val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT;
 
        return val & FB_GFX_FREQ_FUSE_MASK;
@@ -1350,14 +1350,14 @@ static bool chv_rps_enable(struct intel_rps *rps)
                          GEN6_PM_RP_DOWN_TIMEOUT);
 
        /* Setting Fixed Bias */
-       vlv_punit_get(i915);
+       vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
 
        val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
-       vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val);
+       vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val);
 
-       val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
 
-       vlv_punit_put(i915);
+       vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
 
        /* RPS code assumes GPLL is used */
        drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
@@ -1375,7 +1375,7 @@ static int vlv_rps_guar_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val, rp1;
 
-       val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE);
 
        rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK;
        rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
@@ -1388,7 +1388,7 @@ static int vlv_rps_max_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val, rp0;
 
-       val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE);
 
        rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
        /* Clamp to max */
@@ -1402,9 +1402,9 @@ static int vlv_rps_rpe_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val, rpe;
 
-       val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
        rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
-       val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
        rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
 
        return rpe;
@@ -1415,7 +1415,7 @@ static int vlv_rps_min_freq(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 val;
 
-       val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff;
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_LFM) & 0xff;
        /*
         * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
         * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
@@ -1451,15 +1451,15 @@ static bool vlv_rps_enable(struct intel_rps *rps)
        /* WaGsvRC0ResidencyMethod:vlv */
        rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED;
 
-       vlv_punit_get(i915);
+       vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
 
        /* Setting Fixed Bias */
        val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
-       vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val);
+       vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val);
 
-       val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
 
-       vlv_punit_put(i915);
+       vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
 
        /* RPS code assumes GPLL is used */
        drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
@@ -2107,9 +2107,9 @@ static u32 __read_cagf(struct intel_rps *rps, bool take_fw)
        } else if (GRAPHICS_VER(i915) >= 12) {
                r = GEN12_RPSTAT1;
        } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
-               vlv_punit_get(i915);
-               freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
-               vlv_punit_put(i915);
+               vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
+               freq = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
+               vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
        } else if (GRAPHICS_VER(i915) >= 6) {
                r = GEN6_RPSTAT1;
        } else {
index 0b92ab4e9fb9bbe96373c3de78800c209f88629a..e8d6bd116b446045803e317308afe5e5e682d7d8 100644 (file)
@@ -98,7 +98,7 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915)
        u32 val;
 
        vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
-       val = vlv_cck_read(i915, CCK_FUSE_REG);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCK, CCK_FUSE_REG);
        vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
 
        switch ((val >> 2) & 0x7) {
@@ -114,7 +114,7 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
        u32 val;
 
        vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
-       val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+       val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS);
        vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
 
        switch ((val >> 6) & 3) {