]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAX
authorJani Nikula <jani.nikula@intel.com>
Wed, 8 May 2024 15:47:48 +0000 (18:47 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 10 May 2024 08:23:47 +0000 (11:23 +0300)
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VRR_VMAX register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6256642f1943b87650fdf600ef08f6d3b8617a87.1715183162.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_vrr.c
drivers/gpu/drm/i915/i915_reg.h

index b1136aee775f5f377547be961f9c02d82d192858..d9024ccf6098d47e3df90ff2a680a9dab83f690a 100644 (file)
@@ -219,7 +219,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
        }
 
        intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
-       intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
+       intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
+                      crtc_state->vrr.vmax - 1);
        intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
                       trans_vrr_ctl(crtc_state));
        intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
@@ -309,7 +310,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
        if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
                crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
-               crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
+               crtc_state->vrr.vmax = intel_de_read(dev_priv,
+                                                    TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1;
                crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
        }
 
index 7c4a24d73d39115b5f02de03e547cd028f5ba950..e24a6998babd3acff4cb5ef57f83d318202ff450 100644 (file)
 #define _TRANS_VRR_VMAX_B              0x61424
 #define _TRANS_VRR_VMAX_C              0x62424
 #define _TRANS_VRR_VMAX_D              0x63424
-#define TRANS_VRR_VMAX(trans)          _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
+#define TRANS_VRR_VMAX(dev_priv, trans)                _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
 #define   VRR_VMAX_MASK                        REG_GENMASK(19, 0)
 
 #define _TRANS_VRR_VMIN_A              0x60434