clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU

Enable auto clock mode, and define the additional fields which are used
when this mode is enabled.

/sys/kernel/debug/clk/clk_summary now reports approximately 308 running
clocks and 298 disabled clocks. Prior to this commit 586 clocks were
running and 17 disabled.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251222-automatic-clocks-v7-4-fec86fa89874@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 70b26db9b95ad0b376d23f637c7683fbc8c8c600..8551289b46eb88ec61dd1914d0fe782ae6794000 100644 (file)
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -26,6 +26,10 @@
 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
 
+#define GS101_GATE_DBG_OFFSET 0x4000
+#define GS101_DRCG_EN_OFFSET  0x104
+#define GS101_MEMCLK_OFFSET   0x108
+
 /* ---- CMU_TOP ------------------------------------------------------------- */
 
 /* Register Offset definitions for CMU_TOP (0x1e080000) */
@@ -1433,6 +1437,9 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_TOP,
        .clk_regs               = cmu_top_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(cmu_top_clk_regs),
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .option_offset          = CMU_CMU_TOP_CONTROLLER_OPTION,
 };
 
 static void __init gs101_cmu_top_init(struct device_node *np)
@@ -1900,6 +1907,11 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
             CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
 };
 
+static const unsigned long dcrg_memclk_sysreg[] __initconst = {
+       GS101_DRCG_EN_OFFSET,
+       GS101_MEMCLK_OFFSET,
+};
+
 static const struct samsung_cmu_info apm_cmu_info __initconst = {
        .mux_clks               = apm_mux_clks,
        .nr_mux_clks            = ARRAY_SIZE(apm_mux_clks),
@@ -1912,6 +1924,12 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_APM,
        .clk_regs               = apm_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(apm_clk_regs),
+       .sysreg_clk_regs        = dcrg_memclk_sysreg,
+       .nr_sysreg_clk_regs     = ARRAY_SIZE(dcrg_memclk_sysreg),
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .drcg_offset            = GS101_DRCG_EN_OFFSET,
+       .memclk_offset          = GS101_MEMCLK_OFFSET,
 };
 
 /* ---- CMU_HSI0 ------------------------------------------------------------ */
@@ -2375,7 +2393,14 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_HSI0,
        .clk_regs               = hsi0_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(hsi0_clk_regs),
+       .sysreg_clk_regs        = dcrg_memclk_sysreg,
+       .nr_sysreg_clk_regs     = ARRAY_SIZE(dcrg_memclk_sysreg),
        .clk_name               = "bus",
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .option_offset          = HSI0_CMU_HSI0_CONTROLLER_OPTION,
+       .drcg_offset            = GS101_DRCG_EN_OFFSET,
+       .memclk_offset          = GS101_MEMCLK_OFFSET,
 };
 
 /* ---- CMU_HSI2 ------------------------------------------------------------ */
@@ -2863,7 +2888,14 @@ static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_HSI2,
        .clk_regs               = cmu_hsi2_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(cmu_hsi2_clk_regs),
+       .sysreg_clk_regs        = dcrg_memclk_sysreg,
+       .nr_sysreg_clk_regs     = ARRAY_SIZE(dcrg_memclk_sysreg),
        .clk_name               = "bus",
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .option_offset          = HSI2_CMU_HSI2_CONTROLLER_OPTION,
+       .drcg_offset            = GS101_DRCG_EN_OFFSET,
+       .memclk_offset          = GS101_MEMCLK_OFFSET,
 };
 
 /* ---- CMU_MISC ------------------------------------------------------------ */
@@ -3423,7 +3455,14 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_MISC,
        .clk_regs               = misc_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(misc_clk_regs),
+       .sysreg_clk_regs        = dcrg_memclk_sysreg,
+       .nr_sysreg_clk_regs     = ARRAY_SIZE(dcrg_memclk_sysreg),
        .clk_name               = "bus",
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .option_offset          = MISC_CMU_MISC_CONTROLLER_OPTION,
+       .drcg_offset            = GS101_DRCG_EN_OFFSET,
+       .memclk_offset          = GS101_MEMCLK_OFFSET,
 };
 
 static void __init gs101_cmu_misc_init(struct device_node *np)
@@ -4010,6 +4049,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
             21, 0, 0),
 };
 
+static const unsigned long dcrg_sysreg[] __initconst = {
+       GS101_DRCG_EN_OFFSET,
+};
+
 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
        .mux_clks               = peric0_mux_clks,
        .nr_mux_clks            = ARRAY_SIZE(peric0_mux_clks),
@@ -4020,7 +4063,13 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_PERIC0,
        .clk_regs               = peric0_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(peric0_clk_regs),
+       .sysreg_clk_regs        = dcrg_sysreg,
+       .nr_sysreg_clk_regs     = ARRAY_SIZE(dcrg_sysreg),
        .clk_name               = "bus",
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .option_offset          = PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
+       .drcg_offset            = GS101_DRCG_EN_OFFSET,
 };
 
 /* ---- CMU_PERIC1 ---------------------------------------------------------- */
@@ -4368,7 +4417,13 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
        .nr_clk_ids             = CLKS_NR_PERIC1,
        .clk_regs               = peric1_clk_regs,
        .nr_clk_regs            = ARRAY_SIZE(peric1_clk_regs),
+       .sysreg_clk_regs        = dcrg_sysreg,
+       .nr_sysreg_clk_regs     = ARRAY_SIZE(dcrg_sysreg),
        .clk_name               = "bus",
+       .auto_clock_gate        = true,
+       .gate_dbg_offset        = GS101_GATE_DBG_OFFSET,
+       .option_offset          = PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
+       .drcg_offset            = GS101_DRCG_EN_OFFSET,
 };
 
 /* ---- platform_driver ----------------------------------------------------- */