}
}
-static void acpi_dsdt_add_pci_osc(Aml *dev)
+static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplug)
{
Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
/*
- * Allow OS control for all 5 features:
- * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
+ * Allow OS control for SHPCHotplug, PME, AER, PCIeCapability,
+ * and PCIeHotplug depending on enable_native_pcie_hotplug
*/
- aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
- aml_name("CTRL")));
+ aml_append(ifctx, aml_and(aml_name("CTRL"),
+ aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)),
+ aml_name("CTRL")));
ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
if (is_cxl) {
build_cxl_osc_method(dev);
} else {
- acpi_dsdt_add_pci_osc(dev);
+ acpi_dsdt_add_pci_osc(dev, true);
}
aml_append(scope, dev);
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
- acpi_dsdt_add_pci_osc(dev);
+ acpi_dsdt_add_pci_osc(dev, true);
Aml *dev_res0 = aml_device("%s", "RES0");
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));