net: stmmac: move most PCS register definitions to stmmac_pcs.c

Move most of the PCS register offset definitions to stmmac_pcs.c.
Since stmmac_pcs.c only ever passes zero into the register offset
macros, remove that ability, making them simple constant integer
definitions.

Add appropriate descriptions of the registers, pointing out their
similarity with their IEEE 802.3 counterparts. Make use of the
BMSR definitions for the GMAC_AN_STATUS register and remove the
driver private versions.

Note that BMSR_LSTATUS is non-low-latching, unlike it's 802.3z
counterpart.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Link: https://patch.msgid.link/E1vlmOV-00000006zv5-1CwO@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 2f826fe7229b6470312170b8ff9f17c65ff1b3e5..e827c03ae932629856aba17a2a4463eaa2d897ec 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -2,6 +2,20 @@
 #include "stmmac.h"
 #include "stmmac_pcs.h"
 
+/*
+ * GMAC_AN_STATUS is equivalent to MII_BMSR
+ * GMAC_ANE_ADV is equivalent to 802.3z MII_ADVERTISE
+ * GMAC_ANE_LPA is equivalent to 802.3z MII_LPA
+ * GMAC_ANE_EXP is equivalent to MII_EXPANSION
+ * GMAC_TBI is equivalent to MII_ESTATUS
+ *
+ * ADV, LPA and EXP are only available for the TBI and RTBI modes.
+ */
+#define GMAC_AN_STATUS 0x04    /* AN status */
+#define GMAC_ANE_ADV   0x08    /* ANE Advertisement */
+#define GMAC_ANE_LPA   0x0c    /* ANE link partener ability */
+#define GMAC_TBI       0x14    /* TBI extend status */
+
 static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
 {
        struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
@@ -49,11 +63,11 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
                               struct stmmac_extra_stats *x)
 {
        struct stmmac_pcs *spcs = priv->integrated_pcs;
-       u32 val = readl(spcs->base + GMAC_AN_STATUS(0));
+       u32 val = readl(spcs->base + GMAC_AN_STATUS);
 
        if (status & PCS_ANE_IRQ) {
                x->irq_pcs_ane_n++;
-               if (val & GMAC_AN_STATUS_ANC)
+               if (val & BMSR_ANEGCOMPLETE)
                        dev_info(priv->device,
                                 "PCS ANE process completed\n");
        }
@@ -61,9 +75,9 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
        if (status & PCS_LINK_IRQ) {
                x->irq_pcs_link_n++;
                dev_info(priv->device, "PCS Link %s\n",
-                        val & GMAC_AN_STATUS_LS ? "Up" : "Down");
+                        val & BMSR_LSTATUS ? "Up" : "Down");
 
-               phylink_pcs_change(&spcs->pcs, val & GMAC_AN_STATUS_LS);
+               phylink_pcs_change(&spcs->pcs, val & BMSR_LSTATUS);
        }
 }
 

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index c4e6b242d39066656d86dfe7fdb245a94d34bc06..13ee5bd6c788343b447f062ac0694de43ec0512a 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -16,13 +16,6 @@
 
 /* PCS registers (AN/TBI/SGMII/RGMII) offsets */
 #define GMAC_AN_CTRL(x)                (x)             /* AN control */
-#define GMAC_AN_STATUS(x)      (x + 0x4)       /* AN status */
-
-/* ADV, LPA and EXP are only available for the TBI and RTBI interfaces */
-#define GMAC_ANE_ADV(x)                (x + 0x8)       /* ANE Advertisement */
-#define GMAC_ANE_LPA(x)                (x + 0xc)       /* ANE link partener ability */
-#define GMAC_ANE_EXP(x)                (x + 0x10)      /* ANE expansion */
-#define GMAC_TBI(x)            (x + 0x14)      /* TBI extend status */
 
 /* AN Configuration defines */
 #define GMAC_AN_CTRL_RAN       BIT_U32(9)      /* Restart Auto-Negotiation */
@@ -32,21 +25,6 @@
 #define GMAC_AN_CTRL_LR                BIT_U32(17)     /* Lock to Reference */
 #define GMAC_AN_CTRL_SGMRAL    BIT_U32(18)     /* SGMII RAL Control */
 
-/* AN Status defines */
-#define GMAC_AN_STATUS_LS      BIT_U32(2)      /* Link Status 0:down 1:up */
-#define GMAC_AN_STATUS_ANA     BIT_U32(3)      /* Auto-Negotiation Ability */
-#define GMAC_AN_STATUS_ANC     BIT_U32(5)      /* Auto-Negotiation Complete */
-#define GMAC_AN_STATUS_ES      BIT_U32(8)      /* Extended Status */
-
-/* ADV and LPA defines */
-#define GMAC_ANE_FD            BIT_U32(5)
-#define GMAC_ANE_HD            BIT_U32(6)
-#define GMAC_ANE_PSE           GENMASK_U32(8, 7)
-#define GMAC_ANE_PSE_SHIFT     7
-#define GMAC_ANE_RFE           GENMASK_U32(13, 12)
-#define GMAC_ANE_RFE_SHIFT     12
-#define GMAC_ANE_ACK           BIT_U32(14)
-
 struct stmmac_priv;
 
 struct stmmac_pcs {