]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual...
authorConor Dooley <conor.dooley@microchip.com>
Thu, 30 Apr 2026 10:10:19 +0000 (11:10 +0100)
committerMark Brown <broonie@kernel.org>
Mon, 4 May 2026 13:23:01 +0000 (22:23 +0900)
The core will deal with reads by creating clock cycles itself, there's
no need to generate clock cycles by transmitting garbage data at the
driver level. Further, transmitting garbage data just bricks the transfer
since QSPI doesn't have a dedicated master-out line like MOSI in regular
SPI. I'm not entirely sure if the transfer is bricked because of the
garbage data being transmitted on the bus or because the core loses
track of whether it is supposed to be sending or receiving data.

Fixes: 8f9cf02c88528 ("spi: microchip-core-qspi: Add regular transfers")
CC: stable@vger.kernel.org
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260430-freezing-saloon-95b1f3d9dad0@spud
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-microchip-core-qspi.c

index ffa0f33a0ae0992701cf7b169fd6d56d6d2bc2a7..70215a407b5a32e006b2a68694a377ca18218fff 100644 (file)
@@ -690,18 +690,28 @@ static int mchp_coreqspi_transfer_one(struct spi_controller *ctlr, struct spi_de
                                      struct spi_transfer *t)
 {
        struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
+       bool dual_quad = false;
 
        qspi->tx_len = t->len;
 
+       if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD ||
+                       t->tx_nbits == SPI_NBITS_DUAL ||
+                       t->rx_nbits == SPI_NBITS_DUAL)
+               dual_quad = true;
+
        if (t->tx_buf)
                qspi->txbuf = (u8 *)t->tx_buf;
 
        if (!t->rx_buf) {
                mchp_coreqspi_write_op(qspi);
-       } else {
+       } else if (!dual_quad) {
                qspi->rxbuf = (u8 *)t->rx_buf;
                qspi->rx_len = t->len;
                mchp_coreqspi_write_read_op(qspi);
+       } else {
+               qspi->rxbuf = (u8 *)t->rx_buf;
+               qspi->rx_len = t->len;
+               mchp_coreqspi_read_op(qspi);
        }
 
        return 0;