arm64: dts: renesas: r9a09g057: Add DU and DSI nodes

Add DU and DSI nodes to RZ/V2H(P) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023212314.679303-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 59dc6025749b9ba662af8c7d09f6614e4b42a329..c09578d2c962d757bff6ead5a4d7ebf80e78d5c1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1349,6 +1349,71 @@
                        };
                };
 
+               dsi: dsi@16430000 {
+                       compatible = "renesas,r9a09g057-mipi-dsi";
+                       reg = <0 0x16430000 0 0x20000>;
+                       interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "seq0", "seq1", "vin1", "rcv",
+                                         "ferr", "ppi", "debug";
+                       clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>,
+                                <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>,
+                                <&cpg CPG_MOD 0xeb>;
+                       clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk";
+                       resets = <&cpg 0xd8>, <&cpg 0xd7>;
+                       reset-names = "arst", "prst";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                                       dsi_out: endpoint {
+                                       };
+                               };
+                       };
+               };
+
+               du: display@16460000 {
+                       compatible = "renesas,r9a09g057-du";
+                       reg = <0 0x16460000 0 0x10000>;
+                       interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>,
+                                <&cpg CPG_MOD 0xef>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xdc>;
+                       renesas,vsps = <&vspd 0>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_dsi: endpoint {
+                                               remote-endpoint = <&dsi_in>;
+                                       };
+                               };
+                       };
+               };
+
                fcpvd: fcp@16470000 {
                        compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv";
                        reg = <0 0x16470000 0 0x10000>;