aarch64: Tighten aarch64_simd_mem_operand_p [PR115969]

aarch64_simd_mem_operand_p checked for a memory with a POST_INC
or REG address, but it didn't check what kind of register was
being used.  This meant that it allowed DImode FPRs as well as GPRs.

I wondered about rewriting it to use aarch64_classify_address,
but this one-line fix seemed simpler.  The structure then mirrors
the existing early exit in aarch64_classify_address itself:

  /* On LE, for AdvSIMD, don't support anything other than POST_INC or
     REG addressing.  */
  if (advsimd_struct_p
      && TARGET_SIMD
      && !BYTES_BIG_ENDIAN
      && (code != POST_INC && code != REG))
    return false;

gcc/
	PR target/115969
	* config/aarch64/aarch64.cc (aarch64_simd_mem_operand_p): Require
	the operand to be a legitimate memory_operand.

gcc/testsuite/
	PR target/115969
	* gcc.target/aarch64/pr115969.c: New test.

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 89eb66348f772a7e94f1acde29cd4badfd51fa3d..9e51236ce9fa059ccc6e4fe24335b5fb36692ef8 100644 (file)
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -23377,8 +23377,9 @@ aarch64_endian_lane_rtx (machine_mode mode, unsigned int n)
 bool
 aarch64_simd_mem_operand_p (rtx op)
 {
-  return MEM_P (op) && (GET_CODE (XEXP (op, 0)) == POST_INC
-                       || REG_P (XEXP (op, 0)));
+  return (MEM_P (op)
+         && (GET_CODE (XEXP (op, 0)) == POST_INC || REG_P (XEXP (op, 0)))
+         && memory_operand (op, VOIDmode));
 }
 
 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction.  */

diff --git a/gcc/testsuite/gcc.target/aarch64/pr115969.c b/gcc/testsuite/gcc.target/aarch64/pr115969.c
new file mode 100644 (file)
index 0000000..ea46626
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr115969.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" } */
+
+#define vec8 __attribute__((vector_size(8)))
+vec8 int f(int *a)
+{
+        asm("":"+w"(a));
+        return (vec8 int){a[0], a[0]};
+}