crypto: hisilicon/qm - move the barrier before writing to the mailbox register

Before sending the data via the mailbox to the hardware, to ensure
that the data accessed by the hardware is the most up-to-date,
a write barrier should be added before writing to the mailbox register.
The current memory barrier is placed after writing to the register,
the barrier order should be modified to be before writing to the register.

Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index 700fc1b8318ed3cd00bf72cafed6e0d36cf207c7..49c1c78ff600b97c88cdc0e2c414cc1d6b2c7e82 100644 (file)
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -609,9 +609,13 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
        }
 
 #if IS_ENABLED(CONFIG_ARM64)
+       /*
+        * The dmb oshst instruction ensures that the data in the
+        * mailbox is written before it is sent to the hardware.
+        */
        asm volatile("ldp %0, %1, %3\n"
-                    "stp %0, %1, %2\n"
                     "dmb oshst\n"
+                    "stp %0, %1, %2\n"
                     : "=&r" (tmp0),
                       "=&r" (tmp1),
                       "+Q" (*((char __iomem *)fun_base))