]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
iio: accel: adxl313: make use of regmap cache
authorLothar Rubusch <l.rubusch@gmail.com>
Wed, 2 Jul 2025 23:08:12 +0000 (23:08 +0000)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 13 Jul 2025 14:36:26 +0000 (15:36 +0100)
Setup regmap cache to cache register configuration, reducing bus traffic
for repeated accesses to non volatile registers.

Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20250702230819.19353-2-l.rubusch@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
drivers/iio/accel/adxl313.h
drivers/iio/accel/adxl313_core.c
drivers/iio/accel/adxl313_i2c.c
drivers/iio/accel/adxl313_spi.c

index 72f624af46862d71ec09fd89f47a04ecb407eeef..2bc86ac8ffd4456618610e882337c80486dd28f5 100644 (file)
@@ -22,6 +22,7 @@
 #define ADXL313_REG_BW_RATE            0x2C
 #define ADXL313_REG_POWER_CTL          0x2D
 #define ADXL313_REG_INT_MAP            0x2F
+#define ADXL313_REG_INT_SOURCE         0x30
 #define ADXL313_REG_DATA_FORMAT                0x31
 #define ADXL313_REG_DATA_AXIS(index)   (0x32 + ((index) * 2))
 #define ADXL313_REG_FIFO_CTL           0x38
@@ -54,6 +55,8 @@ extern const struct regmap_access_table adxl312_writable_regs_table;
 extern const struct regmap_access_table adxl313_writable_regs_table;
 extern const struct regmap_access_table adxl314_writable_regs_table;
 
+bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg);
+
 enum adxl313_device_type {
        ADXL312,
        ADXL313,
index 8996180f1e18e2cea45f1ddecf50674cc389de96..dc5f04b17b2930d9bbe975d9f889cfc35ac2ade7 100644 (file)
@@ -46,6 +46,24 @@ const struct regmap_access_table adxl314_readable_regs_table = {
 };
 EXPORT_SYMBOL_NS_GPL(adxl314_readable_regs_table, "IIO_ADXL313");
 
+bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg)
+{
+       switch (reg) {
+       case ADXL313_REG_DATA_AXIS(0):
+       case ADXL313_REG_DATA_AXIS(1):
+       case ADXL313_REG_DATA_AXIS(2):
+       case ADXL313_REG_DATA_AXIS(3):
+       case ADXL313_REG_DATA_AXIS(4):
+       case ADXL313_REG_DATA_AXIS(5):
+       case ADXL313_REG_FIFO_STATUS:
+       case ADXL313_REG_INT_SOURCE:
+               return true;
+       default:
+               return false;
+       }
+}
+EXPORT_SYMBOL_NS_GPL(adxl313_is_volatile_reg, "IIO_ADXL313");
+
 static int adxl312_check_id(struct device *dev,
                            struct adxl313_data *data)
 {
index dfa51860cd83d60b06500dbbc574763c56fc3cf4..b67ff0b4dc5474a8069f39efd02dc63499d573b3 100644 (file)
@@ -21,6 +21,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
                .rd_table       = &adxl312_readable_regs_table,
                .wr_table       = &adxl312_writable_regs_table,
                .max_register   = 0x39,
+               .volatile_reg   = adxl313_is_volatile_reg,
+               .cache_type     = REGCACHE_MAPLE,
        },
        [ADXL313] = {
                .reg_bits       = 8,
@@ -28,6 +30,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
                .rd_table       = &adxl313_readable_regs_table,
                .wr_table       = &adxl313_writable_regs_table,
                .max_register   = 0x39,
+               .volatile_reg   = adxl313_is_volatile_reg,
+               .cache_type     = REGCACHE_MAPLE,
        },
        [ADXL314] = {
                .reg_bits       = 8,
@@ -35,6 +39,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
                .rd_table       = &adxl314_readable_regs_table,
                .wr_table       = &adxl314_writable_regs_table,
                .max_register   = 0x39,
+               .volatile_reg   = adxl313_is_volatile_reg,
+               .cache_type     = REGCACHE_MAPLE,
        },
 };
 
index ebc5d09f108d16f263065d8b14671b7fb1ee8b14..dedb0885c2772551c0046f3199cbfafbfa937335 100644 (file)
@@ -24,6 +24,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
                .max_register   = 0x39,
                /* Setting bits 7 and 6 enables multiple-byte read */
                .read_flag_mask = BIT(7) | BIT(6),
+               .volatile_reg   = adxl313_is_volatile_reg,
+               .cache_type     = REGCACHE_MAPLE,
        },
        [ADXL313] = {
                .reg_bits       = 8,
@@ -33,6 +35,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
                .max_register   = 0x39,
                /* Setting bits 7 and 6 enables multiple-byte read */
                .read_flag_mask = BIT(7) | BIT(6),
+               .volatile_reg   = adxl313_is_volatile_reg,
+               .cache_type     = REGCACHE_MAPLE,
        },
        [ADXL314] = {
                .reg_bits       = 8,
@@ -42,6 +46,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
                .max_register   = 0x39,
                /* Setting bits 7 and 6 enables multiple-byte read */
                .read_flag_mask = BIT(7) | BIT(6),
+               .volatile_reg   = adxl313_is_volatile_reg,
+               .cache_type     = REGCACHE_MAPLE,
        },
 };