arm64: dts: qcom: qcs8300: Add support for camss

Add changes to support the camera subsystem on the QCS8300.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251107162521.511536-3-quic_vikramsa@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 96bfc35f955ee15688b89e525e62872ce21a54ba..e7b12b01928d66a5398c3f8c3bedc0ab38bdd76e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4784,6 +4784,178 @@
                        #power-domain-cells = <1>;
                };
 
+               camss: isp@ac78000 {
+                       compatible = "qcom,qcs8300-camss";
+
+                       reg = <0x0 0xac78000 0x0 0x1000>,
+                             <0x0 0xac7a000 0x0 0xf00>,
+                             <0x0 0xac7c000 0x0 0xf00>,
+                             <0x0 0xac84000 0x0 0xf00>,
+                             <0x0 0xac88000 0x0 0xf00>,
+                             <0x0 0xac8c000 0x0 0xf00>,
+                             <0x0 0xac90000 0x0 0xf00>,
+                             <0x0 0xac94000 0x0 0xf00>,
+                             <0x0 0xac9c000 0x0 0x2000>,
+                             <0x0 0xac9e000 0x0 0x2000>,
+                             <0x0 0xaca0000 0x0 0x2000>,
+                             <0x0 0xacac000 0x0 0x400>,
+                             <0x0 0xacad000 0x0 0x400>,
+                             <0x0 0xacae000 0x0 0x400>,
+                             <0x0 0xac4d000 0x0 0xf000>,
+                             <0x0 0xac60000 0x0 0xf000>,
+                             <0x0 0xac85000 0x0 0xd00>,
+                             <0x0 0xac89000 0x0 0xd00>,
+                             <0x0 0xac8d000 0x0 0xd00>,
+                             <0x0 0xac91000 0x0 0xd00>,
+                             <0x0 0xac95000 0x0 0xd00>;
+                       reg-names = "csid_wrapper",
+                                   "csid0",
+                                   "csid1",
+                                   "csid_lite0",
+                                   "csid_lite1",
+                                   "csid_lite2",
+                                   "csid_lite3",
+                                   "csid_lite4",
+                                   "csiphy0",
+                                   "csiphy1",
+                                   "csiphy2",
+                                   "tpg0",
+                                   "tpg1",
+                                   "tpg2",
+                                   "vfe0",
+                                   "vfe1",
+                                   "vfe_lite0",
+                                   "vfe_lite1",
+                                   "vfe_lite2",
+                                   "vfe_lite3",
+                                   "vfe_lite4";
+
+                       clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                                <&camcc CAM_CC_CORE_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+                                <&camcc CAM_CC_CSID_CLK>,
+                                <&camcc CAM_CC_CSIPHY0_CLK>,
+                                <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY1_CLK>,
+                                <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY2_CLK>,
+                                <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+                                <&gcc GCC_CAMERA_HF_AXI_CLK>,
+                                <&gcc GCC_CAMERA_SF_AXI_CLK>,
+                                <&camcc CAM_CC_ICP_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_0_CLK>,
+                                <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_1_CLK>,
+                                <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+                       clock-names = "camnoc_axi",
+                                     "core_ahb",
+                                     "cpas_ahb",
+                                     "cpas_fast_ahb_clk",
+                                     "cpas_vfe_lite",
+                                     "cpas_vfe0",
+                                     "cpas_vfe1",
+                                     "csid",
+                                     "csiphy0",
+                                     "csiphy0_timer",
+                                     "csiphy1",
+                                     "csiphy1_timer",
+                                     "csiphy2",
+                                     "csiphy2_timer",
+                                     "csiphy_rx",
+                                     "gcc_axi_hf",
+                                     "gcc_axi_sf",
+                                     "icp_ahb",
+                                     "vfe0",
+                                     "vfe0_fast_ahb",
+                                     "vfe1",
+                                     "vfe1_fast_ahb",
+                                     "vfe_lite",
+                                     "vfe_lite_ahb",
+                                     "vfe_lite_cphy_rx",
+                                     "vfe_lite_csid";
+
+                       interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "csid0",
+                                         "csid1",
+                                         "csid_lite0",
+                                         "csid_lite1",
+                                         "csid_lite2",
+                                         "csid_lite3",
+                                         "csid_lite4",
+                                         "csiphy0",
+                                         "csiphy1",
+                                         "csiphy2",
+                                         "tpg0",
+                                         "tpg1",
+                                         "tpg2",
+                                         "vfe0",
+                                         "vfe1",
+                                         "vfe_lite0",
+                                         "vfe_lite1",
+                                         "vfe_lite2",
+                                         "vfe_lite3",
+                                         "vfe_lite4";
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "ahb",
+                                            "hf_0";
+
+                       iommus = <&apps_smmu 0x2400 0x20>;
+
+                       power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+                       power-domain-names = "top";
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                               };
+                       };
+               };
+
                camcc: clock-controller@ade0000 {
                        compatible = "qcom,qcs8300-camcc";
                        reg = <0x0 0x0ade0000 0x0 0x20000>;