arm64: dts: qcom: sm6125: Add debug UART node

qup0 on sm6125 has 6 SEs and SE4 is used as debug uart. The uart node
and the associated pinctrl are added here.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://lore.kernel.org/r/20260121-xiaomi-ginkgo-features-v2-3-fb3ee94922d0@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 16a65b3c87eb32e3ec60934050e284a0587d6a7b..c84911a98fce9bca3e77261eb7e45674e2d011f8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -661,6 +661,13 @@
                                drive-strength = <6>;
                                bias-disable;
                        };
+
+                       qup_uart4_default: qup-uart4-default-state {
+                               pins = "gpio16", "gpio17";
+                               function = "qup04";
+                               drive-strength = <2>;
+                               bias-disable;
+                       };
                };
 
                gcc: clock-controller@1400000 {
@@ -985,6 +992,17 @@
                                #size-cells = <0>;
                                status = "disabled";
                        };
+
+                       uart4: serial@4a90000 {
+                               compatible = "qcom,geni-debug-uart";
+                               reg = <0x04a90000 0x4000>;
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+                               clock-names = "se";
+                               interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-0 = <&qup_uart4_default>;
+                               pinctrl-names = "default";
+                               status = "disabled";
+                       };
                };
 
                gpi_dma1: dma-controller@4c00000 {