phy: qcom-qmp: pcs-pcie: Add v8 register offsets

Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new
PCS PCIE specific offsets in a dedicated header file.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-3-d04ee9cca83b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h
new file mode 100644 (file)
index 0000000..1e06aa9
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V8_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V8_H_
+
+/* Only for QMP V8 PHY - PCIE PCS registers */
+
+#define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG2           0x00c
+#define QPHY_PCIE_V8_PCS_TX_RX_CONFIG          0x018
+#define QPHY_PCIE_V8_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
+#define QPHY_PCIE_V8_PCS_OSC_DTCT_ACTIONS              0x090
+#define QPHY_PCIE_V8_PCS_EQ_CONFIG1                    0x0a0
+#define QPHY_PCIE_V8_PCS_G3_RXEQEVAL_TIME              0x0f0
+#define QPHY_PCIE_V8_PCS_G4_RXEQEVAL_TIME              0x0f4
+#define QPHY_PCIE_V8_PCS_G4_EQ_CONFIG5         0x108
+#define QPHY_PCIE_V8_PCS_G4_PRE_GAIN                   0x15c
+#define QPHY_PCIE_V8_PCS_G12S1_TXDEEMPH_M6DB                   0x170
+#define QPHY_PCIE_V8_PCS_G3S2_PRE_GAIN                 0x178
+#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG1  0x17c
+#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG3  0x184
+#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG5  0x18c
+#define QPHY_PCIE_V8_PCS_RX_SIGDET_LVL                 0x190
+#define QPHY_PCIE_V8_PCS_G3_FOM_EQ_CONFIG5             0x1ac
+#define QPHY_PCIE_V8_PCS_ELECIDLE_DLY_SEL                      0x1b8
+#define QPHY_PCIE_V8_PCS_G4_FOM_EQ_CONFIG5             0x1c0
+#define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6                   0x1d0
+#define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG1                     0x1dc
+#define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG2                     0x1e0
+#define QPHY_PCIE_V8_PCS_EQ_CONFIG4                    0x1f8
+#define QPHY_PCIE_V8_PCS_EQ_CONFIG5                    0x1fc
+#endif