[pci] Add definitions for PCI Express function level reset (FLR)

Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/drivers/net/tg3/tg3.h b/src/drivers/net/tg3/tg3.h
index 2b85b065b1cee3b68179ff56eb25717e4da58b44..bfabad0713d585457a28a8bbfbc03ca22b7cbc6d 100644 (file)
--- a/src/drivers/net/tg3/tg3.h
+++ b/src/drivers/net/tg3/tg3.h
@@ -52,7 +52,6 @@
 #define PCI_X_CMD                      2       /* Modes & Features */
 #define PCI_X_CMD_ERO                  0x0002  /* Enable Relaxed Ordering */
 
-#define PCI_EXP_DEVCTL                 8       /* Device Control */
 #define PCI_EXP_DEVCTL_RELAX_EN                0x0010 /* Enable relaxed ordering */
 #define PCI_EXP_DEVCTL_NOSNOOP_EN      0x0800  /* Enable No Snoop */
 #define PCI_EXP_DEVCTL_PAYLOAD         0x00e0  /* Max_Payload_Size */

diff --git a/src/include/ipxe/pci.h b/src/include/ipxe/pci.h
index a841e00ff79ed6ce1f78d54ecc254d07c0985cc1..89d9d80409d4df843824a21616a7ab8057d74460 100644 (file)
--- a/src/include/ipxe/pci.h
+++ b/src/include/ipxe/pci.h
@@ -104,6 +104,10 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
 #define PCI_PM_CTRL_PME_ENABLE         0x0100  /**< PME pin enable */
 #define PCI_PM_CTRL_PME_STATUS         0x8000  /**< PME pin status */
 
+/** PCI Express */
+#define PCI_EXP_DEVCTL         0x08
+#define PCI_EXP_DEVCTL_FLR             0x8000  /**< Function level reset */
+
 /** Uncorrectable error status */
 #define PCI_ERR_UNCOR_STATUS   0x04
 
@@ -128,6 +132,9 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
        ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) |     \
          ( ( (progif) & 0xff) << 0 ) )
 
+/** PCI Express function level reset delay (in ms) */
+#define PCI_EXP_FLR_DELAY_MS 100
+
 /** A PCI device ID list entry */
 struct pci_device_id {
        /** Name */