{
Int i;
IRSB* bbOut;
- Bool x86busLocked = False;
+ Bool x86busLocked = False;
+ Bool isSnoopedStore = False;
if (gWordTy != hWordTy) {
/* We don't currently support this case. */
switch (st->Ist.MBE.event) {
case Imbe_Fence:
break; /* not interesting */
+ /* Imbe_Bus{Lock,Unlock} arise from x86/amd64 LOCK
+ prefixed instructions. */
case Imbe_BusLock:
tl_assert(x86busLocked == False);
x86busLocked = True;
tl_assert(x86busLocked == True);
x86busLocked = False;
break;
+ /* Imbe_SnoopedStore{Begin,End} arise from ppc
+ stwcx. instructions. */
case Imbe_SnoopedStoreBegin:
+ tl_assert(isSnoopedStore == False);
+ isSnoopedStore = True;
+ break;
case Imbe_SnoopedStoreEnd:
- /* These arise from ppc stwcx. insns. They should
- perhaps be handled better. */
+ tl_assert(isSnoopedStore == True);
+ isSnoopedStore = False;
break;
default:
goto unhandled;
break;
case Ist_Store:
- if (!x86busLocked)
+ if (!x86busLocked && !isSnoopedStore)
instrument_mem_access(
bbOut,
st->Ist.Store.addr,
sizeofIRType(hWordTy)
);
}
+ /* This isn't really correct. Really the
+ instrumentation should be only added when
+ (!x86busLocked && !isSnoopedStore), just like with
+ Ist_Store. Still, I don't think this is
+ particularly important. */
if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify) {
instrument_mem_access(
bbOut, d->mAddr, dataSize, True/*isStore*/,