RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1...

Add asm dump check and run test for vec_duplicate + vmacc.vvm
combine to vmacc.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vx combine.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 4e1a575f2c235e73bde1637c063d06e37122c127..e99744c037bb7e4c1c980952a155ea97fd5ea80f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int16_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 4c4f72dd994f5c0b27a31ee5158443c80f8a7ebe..1f1f3d28d1358e0065dd17bf347f6b05cc3d0897 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int32_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index abf62c2b7f26eb30d617f6391db531121e9d939d..f6bbfaea4386a49fff0a32dfe21f872eff726d20 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int64_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -24,3 +26,4 @@ TEST_BINARY_VX_SIGNED_0(T)
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
    } } } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 7744bcb6e27d37df7b417d843ac2c96c632ff216..d9fd498bc3daf52a0030e3509093ed1da92362a6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int8_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 05801a9c66c2ad9dff3ca08cd2e1dfdcf8ce0328..5ddcc2d0767a3fed14282209d713605858859c06 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int16_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index f05f091d2cc4c26ef096c525a69e1c096e793597..1b25d79ae55e1c2d1818ca27c996577d3d711529 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int32_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index adf9ccb1cd00f496ec490978593ec1e57e0d028f..71507859bc88e77ae1507b71cf41f4012d6e0158 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int64_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 8b3f5bcf24f0c62489fe8ea00c94150ad6c67476..077fab91d8c49c1ced656bee9bc3f3a6957b952a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int8_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 741f431b149786db9290d3fb3c64b33239c78031..056f2c02c6b33014be68519d68c94dcc48dc4431 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int16_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 1741c22666f80ab540e94221c7e0dc54bc794fb0..f36939431d7795c542459de06d490ee07fcde468 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int32_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index d3263574f329078683da3c5a4420a5de775fb897..bc00c6bc72714208a0b13a909e5e4f76cec4d693 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int64_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 3137dc0fb20706280de67d025abf939653dc58fa..15716f682270c5761f52f3039b31cea6f1469333 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -2,10 +2,12 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
 
 #include "vx_binary.h"
+#include "vx_ternary.h"
 
 #define T int8_t
 
 TEST_BINARY_VX_SIGNED_0(T)
+TEST_TERNARY_VX_SIGNED_0(T)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -21,3 +23,4 @@ TEST_BINARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vsadd.vx} } } */
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
new file mode 100644 (file)
index 0000000..be54a3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -0,0 +1,35 @@
+#ifndef HAVE_DEFINED_VX_VF_TERNARY_H
+#define HAVE_DEFINED_VX_VF_TERNARY_H
+
+#include <stdint.h>
+
+#undef HAS_INT128
+
+#if __riscv_xlen == 64
+#define HAS_INT128
+typedef unsigned __int128 uint128_t;
+typedef signed __int128 int128_t;
+#endif
+
+#define DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME)                        \
+void                                                                      \
+test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict vs2, \
+                                       T rs1, unsigned n)                 \
+{                                                                         \
+  for (unsigned i = 0; i < n; i++)                                        \
+    vd[i] = vd[i] OP_2 vs2[i] OP_1 rs1;                                   \
+}
+#define DEF_VX_TERNARY_CASE_0_WRAP(T, OP_1, OP_2, NAME) \
+  DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME)
+#define RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n) \
+  test_vx_ternary_##NAME##_##T##_case_0 (vd, vs2, rs1, n)
+#define RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n)
+
+#define TEST_TERNARY_VX_SIGNED_0(T)                                \
+  DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
+
+#define TEST_TERNARY_VX_UNSIGNED_0(T)                              \
+  DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
+
+#endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
new file mode 100644 (file)
index 0000000..8fed997
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
@@ -0,0 +1,377 @@
+#ifndef HAVE_DEFINED_VX_TERNARY_DATA_H
+#define HAVE_DEFINED_VX_TERNARY_DATA_H
+
+#define N 16
+
+#define TEST_TERNARY_DATA(T, NAME)      test_##T##_##NAME##_data
+#define TEST_TERNARY_DATA_WRAP(T, NAME) TEST_TERNARY_DATA(T, NAME)
+
+int8_t TEST_TERNARY_DATA(int8_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 127 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+         0,    0,    0,    0,
+      -128, -128, -128, -128,
+    },
+    {
+       127,  127,  127,  127,
+       121,  121,  121,  121,
+         8,    8,    8,    8,
+      -126, -126, -126, -126,
+    },
+  },
+};
+
+int16_t TEST_TERNARY_DATA(int16_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 32767 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+           0,      0,      0,      0,
+      -32768, -32768, -32768, -32768,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       32761,  32761,  32761,  32761,
+           8,      8,      8,      8,
+      -32766, -32766, -32766, -32766,
+    },
+  },
+};
+
+int32_t TEST_TERNARY_DATA(int32_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 2147483647 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+                0,           0,           0,           0,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483641,  2147483641,  2147483641,  2147483641,
+                8,           8,           8,           8,
+      -2147483646, -2147483646, -2147483646, -2147483646,
+    },
+  },
+};
+
+int64_t TEST_TERNARY_DATA(int64_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 9223372036854775807ull }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                            2,                       2,                       2,                       2,
+                            0,                       0,                       0,                       0,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+       9223372036854775801ull,  9223372036854775801ull,  9223372036854775801ull,  9223372036854775801ull,
+                            8,                       8,                       8,                       8,
+      -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull,
+    },
+  },
+};
+
+uint8_t TEST_TERNARY_DATA(uint8_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       6,  6,  6,  6,
+       3,  3,  3,  3,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+       6,  6,  6,  6,
+       7,  7,  7,  7,
+    },
+  },
+  {
+    { 255 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       5,  5,  5,  5,
+       3,  3,  3,  3,
+       1,  1,  1,  1,
+    },
+    { /* vd */
+       127,  127,  127,  127,
+       255,  255,  255,  255,
+         0,    0,    0,    0,
+       128,  128,  128,  128,
+    },
+    {
+       127,  127,  127,  127,
+       250,  250,  250,  250,
+       253,  253,  253,  253,
+       127,  127,  127,  127,
+    },
+  },
+};
+
+uint16_t TEST_TERNARY_DATA(uint16_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       6,  6,  6,  6,
+       3,  3,  3,  3,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+       6,  6,  6,  6,
+       7,  7,  7,  7,
+    },
+  },
+  {
+    { 65535 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       5,  5,  5,  5,
+       3,  3,  3,  3,
+       1,  1,  1,  1,
+    },
+    { /* vd */
+       32767,  32767,  32767,  32767,
+       65535,  65535,  65535,  65535,
+           0,      0,      0,      0,
+       32768,  32768,  32768,  32768,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       65530,  65530,  65530,  65530,
+       65533,  65533,  65533,  65533,
+       32767,  32767,  32767,  32767,
+    },
+  },
+};
+
+uint32_t TEST_TERNARY_DATA(uint32_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       6,  6,  6,  6,
+       3,  3,  3,  3,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+       6,  6,  6,  6,
+       7,  7,  7,  7,
+    },
+  },
+  {
+    { 4294967295 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       5,  5,  5,  5,
+       3,  3,  3,  3,
+       1,  1,  1,  1,
+    },
+    { /* vd */
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967295,  4294967295,  4294967295,  4294967295,
+                0,           0,           0,           0,
+       2147483648,  2147483648,  2147483648,  2147483648,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967290,  4294967290,  4294967290,  4294967290,
+       4294967293,  4294967293,  4294967293,  4294967293,
+       2147483647,  2147483647,  2147483647,  2147483647,
+    },
+  },
+};
+
+uint64_t TEST_TERNARY_DATA(uint64_t, macc)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       6,  6,  6,  6,
+       3,  3,  3,  3,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+       6,  6,  6,  6,
+       7,  7,  7,  7,
+    },
+  },
+  {
+    { 18446744073709551615ull }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       5,  5,  5,  5,
+       3,  3,  3,  3,
+       1,  1,  1,  1,
+    },
+    { /* vd */
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+                            0,                       0,                       0,                       0,
+       9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull,
+      18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull,
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+    },
+  },
+};
+
+#endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h
new file mode 100644 (file)
index 0000000..cf1926f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_run.h
@@ -0,0 +1,26 @@
+#ifndef HAVE_DEFINED_VX_TERNARY_RUN_H
+#define HAVE_DEFINED_VX_TERNARY_RUN_H
+
+int
+main ()
+{
+  unsigned i, k;
+
+  for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++)
+    {
+      T rs1 = TEST_DATA[i][0][0];
+      T *vs2 = TEST_DATA[i][1];
+      T *vd = TEST_DATA[i][2];
+      T *expect = TEST_DATA[i][3];
+
+      TEST_RUN (T, NAME, vd, vs2, rs1, N);
+
+      for (k = 0; k < N; k++)
+       if (vd[k] != expect[k])
+         __builtin_abort ();
+    }
+
+  return 0;
+}
+
+#endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c
new file mode 100644 (file)
index 0000000..1310727
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int16_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c
new file mode 100644 (file)
index 0000000..10174cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int32_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c
new file mode 100644 (file)
index 0000000..a33f714
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int64_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c
new file mode 100644 (file)
index 0000000..dbb1c67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int8_t
+#define NAME       macc
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"