clk: sunxi-ng: h6: Set video PLLs limits

Video PLL factors can be set in a way that final PLL rate is outside
stable range. H6 user manual specifically says that N factor should not
be below 12. While it doesn't says anything about maximum stable rate, it
is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).

Set minimum allowed PLL video rate to 288 MHz (12 * 24 MHz) and maximum
to 2.4 GHz, which is maximum in BSP driver.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index e2bc612f1d3ee8c81e3dcbb42b7d8d782a535d9e..139e8389615c74dab720fdfd0e72a24423d7e7ad 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -120,6 +120,8 @@ static struct ccu_nm pll_video0_clk = {
        .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
        .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
        .fixed_post_div = 4,
+       .min_rate       = 288000000,
+       .max_rate       = 2400000000UL,
        .common         = {
                .reg            = 0x040,
                .features       = CCU_FEATURE_FIXED_POSTDIV,
@@ -136,6 +138,8 @@ static struct ccu_nm pll_video1_clk = {
        .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
        .m              = _SUNXI_CCU_DIV(1, 1), /* input divider */
        .fixed_post_div = 4,
+       .min_rate       = 288000000,
+       .max_rate       = 2400000000UL,
        .common         = {
                .reg            = 0x048,
                .features       = CCU_FEATURE_FIXED_POSTDIV,