drm/xe/rtp: Refactor OAG MMIO trigger register whitelisting

Minor refactor of OAG MMIO trigger register whitelisting for code reuse
with OAM MMIO trigger register whitelisting.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20251202025115.373546-5-ashutosh.dixit@intel.com

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 7ca360b2c20d69434158bdd4596c5c6cf53116fc..e8e47aa16a5df70a15b3f5f7f61f1efb9f544704 100644 (file)
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -67,28 +67,6 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
                       ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
        },
-       { XE_RTP_NAME("oa_reg_render"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
-                      ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
-                                  RING_FORCE_TO_NONPRIV_ACCESS_RW),
-                        WHITELIST(OAG_OASTATUS,
-                                  RING_FORCE_TO_NONPRIV_ACCESS_RD),
-                        WHITELIST(OAG_OAHEADPTR,
-                                  RING_FORCE_TO_NONPRIV_ACCESS_RD |
-                                  RING_FORCE_TO_NONPRIV_RANGE_4))
-       },
-       { XE_RTP_NAME("oa_reg_compute"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
-                      ENGINE_CLASS(COMPUTE)),
-         XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
-                                  RING_FORCE_TO_NONPRIV_ACCESS_RW),
-                        WHITELIST(OAG_OASTATUS,
-                                  RING_FORCE_TO_NONPRIV_ACCESS_RD),
-                        WHITELIST(OAG_OAHEADPTR,
-                                  RING_FORCE_TO_NONPRIV_ACCESS_RD |
-                                  RING_FORCE_TO_NONPRIV_RANGE_4))
-       },
        { XE_RTP_NAME("14024997852"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(WHITELIST(FF_MODE,
@@ -96,6 +74,25 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
                         WHITELIST(VFLSKPD,
                                   RING_FORCE_TO_NONPRIV_ACCESS_RW))
        },
+
+#define WHITELIST_OA_MMIO_TRG(trg, status, head) \
+       WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
+       WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
+       WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
+
+#define WHITELIST_OAG_MMIO_TRG \
+       WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
+
+       { XE_RTP_NAME("oag_mmio_trg_rcs"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
+                      ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG)
+       },
+       { XE_RTP_NAME("oag_mmio_trg_ccs"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
+                      ENGINE_CLASS(COMPUTE)),
+         XE_RTP_ACTIONS(WHITELIST_OAG_MMIO_TRG)
+       },
 };
 
 static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)