.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
.config = &glymur_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
- .alloc_dyn_id = true,
.qos_requires_clocks = true,
};
.config = &glymur_aggre3_noc_regmap_config,
.nodes = aggre3_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre3_noc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre4_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(aggre4_noc_nodes),
.bcms = aggre4_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre4_noc_bcms),
- .alloc_dyn_id = true,
.qos_requires_clocks = true,
};
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const hscnoc_bcms[] = {
.num_nodes = ARRAY_SIZE(hscnoc_nodes),
.bcms = hscnoc_bcms,
.num_bcms = ARRAY_SIZE(hscnoc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
.config = &glymur_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
.config = &glymur_lpass_lpicx_noc_regmap_config,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_node * const nsinoc_nodes[] = {
.config = &glymur_nsinoc_regmap_config,
.nodes = nsinoc_nodes,
.num_nodes = ARRAY_SIZE(nsinoc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_node * const oobm_ss_noc_nodes[] = {
.config = &glymur_oobm_ss_noc_regmap_config,
.nodes = oobm_ss_noc_nodes,
.num_nodes = ARRAY_SIZE(oobm_ss_noc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] = {
.num_nodes = ARRAY_SIZE(pcie_east_anoc_nodes),
.bcms = pcie_east_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_east_anoc_bcms),
- .alloc_dyn_id = true,
.qos_requires_clocks = true,
};
.num_nodes = ARRAY_SIZE(pcie_east_slv_noc_nodes),
.bcms = pcie_east_slv_noc_bcms,
.num_bcms = ARRAY_SIZE(pcie_east_slv_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = {
.num_nodes = ARRAY_SIZE(pcie_west_anoc_nodes),
.bcms = pcie_west_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms),
- .alloc_dyn_id = true,
.qos_requires_clocks = true,
};
.num_nodes = ARRAY_SIZE(pcie_west_slv_noc_nodes),
.bcms = pcie_west_slv_noc_bcms,
.num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
- .alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {
if (!qn)
continue;
- if (desc->alloc_dyn_id) {
- if (!qn->node)
- qn->node = icc_node_create_dyn();
- node = qn->node;
- } else {
- node = icc_node_create(qn->id);
- }
+ if (!qn->node)
+ qn->node = icc_node_create_dyn();
+ node = qn->node;
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err_remove_nodes;
node->data = qn;
icc_node_add(node, provider);
- for (j = 0; j < qn->num_links; j++) {
- if (desc->alloc_dyn_id)
- icc_link_nodes(node, &qn->link_nodes[j]->node);
- else
- icc_link_create(node, qn->links[j]);
- }
+ for (j = 0; j < qn->num_links; j++)
+ icc_link_nodes(node, &qn->link_nodes[j]->node);
data->nodes[i] = node;
}
/**
* struct qcom_icc_node - Qualcomm specific interconnect nodes
* @name: the node name used in debugfs
- * @links: an array of nodes where we can go next while traversing
- * @id: a unique node identifier
* @link_nodes: links associated with this node
* @node: icc_node associated with this node
* @num_links: the total number of @links
*/
struct qcom_icc_node {
const char *name;
- u16 links[MAX_LINKS];
- u16 id;
struct icc_node *node;
u16 num_links;
u16 channels;
struct qcom_icc_bcm * const *bcms;
size_t num_bcms;
bool qos_requires_clocks;
- bool alloc_dyn_id;
};
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
.config = &milos_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
.config = &milos_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
- .alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {
};
static const struct qcom_icc_desc qcs615_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc qcs615_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
};
static const struct qcom_icc_desc qcs615_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc qcs615_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
};
static const struct qcom_icc_desc qcs615_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc qcs615_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc qcs615_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc qcs615_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc qcs8300_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
};
static const struct qcom_icc_desc qcs8300_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
- .alloc_dyn_id = true,
.nodes = gpdsp_anoc_nodes,
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
};
static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc qcs8300_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_nspa_noc = {
- .alloc_dyn_id = true,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
};
static const struct qcom_icc_desc qcs8300_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
};
static const struct qcom_icc_desc qcs8300_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc qdu1000_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc qdu1000_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc qdu1000_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc qdu1000_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const config_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
.num_bcms = ARRAY_SIZE(config_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
- .alloc_dyn_id = true,
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
- .alloc_dyn_id = true,
};
static const struct of_device_id qnoc_of_match[] = {
};
static const struct qcom_icc_desc sar2130p_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sar2130p_config_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
};
static const struct qcom_icc_desc sar2130p_gem_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
};
static const struct qcom_icc_desc sar2130p_lpass_ag_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
static const struct qcom_icc_desc sar2130p_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sar2130p_mmss_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
};
static const struct qcom_icc_desc sar2130p_nsp_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
};
static const struct qcom_icc_desc sar2130p_pcie_anoc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
};
static const struct qcom_icc_desc sar2130p_system_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
};
static const struct qcom_icc_desc sc7180_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sc7180_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sc7180_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
};
static const struct qcom_icc_desc sc7180_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
};
static const struct qcom_icc_desc sc7180_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sc7180_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
};
static const struct qcom_icc_desc sc7180_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sc7180_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sc7180_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sc7180_npu_noc = {
- .alloc_dyn_id = true,
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
};
};
static const struct qcom_icc_desc sc7180_qup_virt = {
- .alloc_dyn_id = true,
.nodes = qup_virt_nodes,
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
.bcms = qup_virt_bcms,
};
static const struct qcom_icc_desc sc7180_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sc7280_aggre1_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
};
static const struct qcom_icc_desc sc7280_aggre2_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
};
static const struct qcom_icc_desc sc7280_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sc7280_cnoc2 = {
- .alloc_dyn_id = true,
.config = &sc7280_cnoc2_regmap_config,
.nodes = cnoc2_nodes,
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
};
static const struct qcom_icc_desc sc7280_cnoc3 = {
- .alloc_dyn_id = true,
.config = &sc7280_cnoc3_regmap_config,
.nodes = cnoc3_nodes,
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
};
static const struct qcom_icc_desc sc7280_dc_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
static const struct qcom_icc_desc sc7280_gem_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
};
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
static const struct qcom_icc_desc sc7280_mc_virt = {
- .alloc_dyn_id = true,
.config = &sc7280_mc_virt_regmap_config,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
};
static const struct qcom_icc_desc sc7280_mmss_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
};
static const struct qcom_icc_desc sc7280_nsp_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_nsp_noc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
};
static const struct qcom_icc_desc sc7280_system_noc = {
- .alloc_dyn_id = true,
.config = &sc7280_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
};
static const struct qcom_icc_desc sc8180x_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
};
static const struct qcom_icc_desc sc8180x_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
static const struct qcom_icc_desc sc8180x_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sc8180x_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sc8180x_qup_virt = {
- .alloc_dyn_id = true,
.nodes = qup_virt_nodes,
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
.bcms = qup_virt_bcms,
};
static const struct qcom_icc_desc sc8280xp_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sc8280xp_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sc8280xp_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_nspa_noc = {
- .alloc_dyn_id = true,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_nspb_noc = {
- .alloc_dyn_id = true,
.nodes = nspb_noc_nodes,
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
};
static const struct qcom_icc_desc sc8280xp_system_noc_main = {
- .alloc_dyn_id = true,
.nodes = system_noc_main_nodes,
.num_nodes = ARRAY_SIZE(system_noc_main_nodes),
.bcms = system_noc_main_bcms,
};
static const struct qcom_icc_desc sdm670_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sdm670_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sdm670_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sdm670_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sdm670_gladiator_noc = {
- .alloc_dyn_id = true,
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
};
static const struct qcom_icc_desc sdm670_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
};
static const struct qcom_icc_desc sdm670_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sdm670_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sdm845_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sdm845_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sdm845_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sdm845_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sdm845_gladiator_noc = {
- .alloc_dyn_id = true,
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
};
static const struct qcom_icc_desc sdm845_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
};
static const struct qcom_icc_desc sdm845_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sdm845_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sdx55_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sdx55_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
};
static const struct qcom_icc_desc sdx55_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sdx65_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sdx65_mem_noc = {
- .alloc_dyn_id = true,
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
};
static const struct qcom_icc_desc sdx65_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sdx75_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sdx75_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
};
static const struct qcom_icc_desc sdx75_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sdx75_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sdx75_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
};
static const struct qcom_icc_desc sdx75_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm6350_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sm6350_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm6350_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sm6350_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
};
static const struct qcom_icc_desc sm6350_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm6350_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sm6350_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm6350_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm6350_npu_noc = {
- .alloc_dyn_id = true,
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
.bcms = npu_noc_bcms,
};
static const struct qcom_icc_desc sm6350_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm7150_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sm7150_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm7150_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
};
static const struct qcom_icc_desc sm7150_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
};
static const struct qcom_icc_desc sm7150_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm7150_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sm7150_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm7150_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm7150_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm7150_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm8150_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sm8150_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm8150_camnoc_virt = {
- .alloc_dyn_id = true,
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
};
static const struct qcom_icc_desc sm8150_compute_noc = {
- .alloc_dyn_id = true,
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
};
static const struct qcom_icc_desc sm8150_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm8150_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sm8150_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm8150_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm8150_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm8150_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm8350_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sm8350_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm8350_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm8350_dc_noc = {
- .alloc_dyn_id = true,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
};
static const struct qcom_icc_desc sm8350_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
};
static const struct qcom_icc_desc sm8350_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm8350_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm8350_compute_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
};
static const struct qcom_icc_desc sm8350_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm8450_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sm8450_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm8450_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sm8450_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm8450_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm8450_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
};
static const struct qcom_icc_desc sm8450_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm8450_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm8450_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
};
static const struct qcom_icc_desc sm8450_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
};
static const struct qcom_icc_desc sm8450_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm8550_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc sm8550_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm8550_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sm8550_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm8550_cnoc_main = {
- .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
};
static const struct qcom_icc_desc sm8550_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
};
static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
};
static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
};
static const struct qcom_icc_desc sm8550_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm8550_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm8550_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
};
static const struct qcom_icc_desc sm8550_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
};
static const struct qcom_icc_desc sm8550_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc sm8650_aggre1_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
};
static const struct qcom_icc_desc sm8650_aggre2_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
};
static const struct qcom_icc_desc sm8650_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sm8650_config_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
};
static const struct qcom_icc_desc sm8650_cnoc_main = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
};
static const struct qcom_icc_desc sm8650_gem_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
};
static const struct qcom_icc_desc sm8650_lpass_ag_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
};
static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
};
static const struct qcom_icc_desc sm8650_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm8650_mmss_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
};
static const struct qcom_icc_desc sm8650_nsp_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
};
static const struct qcom_icc_desc sm8650_pcie_anoc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
};
static const struct qcom_icc_desc sm8650_system_noc = {
- .alloc_dyn_id = true,
.config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
};
static const struct qcom_icc_desc sm8750_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
};
};
static const struct qcom_icc_desc sm8750_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc sm8750_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc sm8750_config_noc = {
- .alloc_dyn_id = true,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
};
static const struct qcom_icc_desc sm8750_cnoc_main = {
- .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
};
static const struct qcom_icc_desc sm8750_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc sm8750_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
};
static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
};
static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
};
};
static const struct qcom_icc_desc sm8750_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc sm8750_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc sm8750_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
};
static const struct qcom_icc_desc sm8750_pcie_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
};
static const struct qcom_icc_desc sm8750_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_aggre1_noc = {
- .alloc_dyn_id = true,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_aggre2_noc = {
- .alloc_dyn_id = true,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_clk_virt = {
- .alloc_dyn_id = true,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
};
static const struct qcom_icc_desc x1e80100_cnoc_cfg = {
- .alloc_dyn_id = true,
.nodes = cnoc_cfg_nodes,
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
.bcms = cnoc_cfg_bcms,
};
static const struct qcom_icc_desc x1e80100_cnoc_main = {
- .alloc_dyn_id = true,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
};
static const struct qcom_icc_desc x1e80100_gem_noc = {
- .alloc_dyn_id = true,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
- .alloc_dyn_id = true,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
.bcms = lpass_lpicx_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_mc_virt = {
- .alloc_dyn_id = true,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
};
static const struct qcom_icc_desc x1e80100_mmss_noc = {
- .alloc_dyn_id = true,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_nsp_noc = {
- .alloc_dyn_id = true,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_center_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),
.bcms = pcie_center_anoc_bcms,
};
static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_north_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),
.bcms = pcie_north_anoc_bcms,
};
static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
- .alloc_dyn_id = true,
.nodes = pcie_south_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),
.bcms = pcie_south_anoc_bcms,
};
static const struct qcom_icc_desc x1e80100_system_noc = {
- .alloc_dyn_id = true,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
};
static const struct qcom_icc_desc x1e80100_usb_center_anoc = {
- .alloc_dyn_id = true,
.nodes = usb_center_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),
.bcms = usb_center_anoc_bcms,
};
static const struct qcom_icc_desc x1e80100_usb_north_anoc = {
- .alloc_dyn_id = true,
.nodes = usb_north_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),
.bcms = usb_north_anoc_bcms,
};
static const struct qcom_icc_desc x1e80100_usb_south_anoc = {
- .alloc_dyn_id = true,
.nodes = usb_south_anoc_nodes,
.num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),
.bcms = usb_south_anoc_bcms,