AC100_CLKOUT_DIV_WIDTH);
}
-static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
-{
- unsigned long best_rate = 0, tmp_rate, tmp_prate;
- int i;
-
- if (prate == AC100_RTC_32K_RATE)
- return divider_round_rate(hw, rate, &prate, NULL,
- AC100_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_POWER_OF_TWO);
-
- for (i = 0; ac100_clkout_prediv[i].div; i++) {
- tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
- tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,
- AC100_CLKOUT_DIV_WIDTH,
- CLK_DIVIDER_POWER_OF_TWO);
-
- if (tmp_rate > rate)
- continue;
- if (rate - tmp_rate < best_rate - tmp_rate)
- best_rate = tmp_rate;
- }
-
- return best_rate;
-}
-
static int ac100_clkout_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
- struct clk_hw *best_parent;
+ int i, ret, num_parents = clk_hw_get_num_parents(hw);
+ struct clk_hw *best_parent = NULL;
unsigned long best = 0;
- int i, num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
- unsigned long tmp, prate;
+ unsigned long prate;
/*
* The clock has two parents, one is a fixed clock which is
prate = clk_hw_get_rate(parent);
- tmp = ac100_clkout_round_rate(hw, req->rate, prate);
-
- if (tmp > req->rate)
- continue;
- if (req->rate - tmp < req->rate - best) {
- best = tmp;
- best_parent = parent;
+ if (prate == AC100_RTC_32K_RATE) {
+ struct clk_rate_request div_req = *req;
+
+ div_req.best_parent_rate = prate;
+
+ ret = divider_determine_rate(hw, &div_req, NULL,
+ AC100_CLKOUT_DIV_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO);
+ if (ret != 0 || div_req.rate > req->rate) {
+ continue;
+ } else if (req->rate - div_req.rate < req->rate - best) {
+ best = div_req.rate;
+ best_parent = parent;
+ }
+ } else {
+ int j;
+
+ for (j = 0; ac100_clkout_prediv[j].div; j++) {
+ struct clk_rate_request div_req = *req;
+ unsigned long tmp_prate;
+
+ tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[j].div);
+ div_req.best_parent_rate = tmp_prate;
+
+ ret = divider_determine_rate(hw, &div_req, NULL,
+ AC100_CLKOUT_DIV_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO);
+ if (ret != 0 || div_req.rate > req->rate) {
+ continue;
+ } else if (req->rate - div_req.rate < req->rate - best) {
+ best = div_req.rate;
+ best_parent = parent;
+ }
+ }
}
}
return -EINVAL;
req->best_parent_hw = best_parent;
- req->best_parent_rate = best;
+ req->best_parent_rate = clk_hw_get_rate(best_parent);
req->rate = best;
return 0;