More RISC-V testsuite hygiene

More testsuite hygiene.  Some of the thead tests are expecting to find
xtheadvdot in the extension set, but it's not defined as a valid extension
anywhere.  I'm just removing xtheadvdot.  Someone more familiar with these
cores can add it back properly if they're so inclined.

Second, there's a space after the zifencei in a couple of the thead arch
strings.  Naturally that causes failures as well.  That's a trivial fix, just
remove the bogus whitespace.

That gets us clean on riscv.exp on the pioneer system.

The pioneer is happy, as is riscv32-elf and riscv64-elf.  Pushing to the trunk.

gcc/
	* config/riscv/riscv-cores.def (xt-c908v): Drop xtheadvdot.
	(xt-c910v2): Remove extraenous whitespace.
	(xt-c920v2): Drop xtheadvdot and remove extraeonous whitespace.

gcc/testsuite/

	* gcc.target/riscv/mcpu-xt-c908v.c: Drop xtheadvdot.
	* gcc.target/riscv/mcpu-xt-c920v2.c: Drop xtheadvdot.

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 98f347034fbb659ba2a593680922d0ce1be2c367..8f0f63078ffcf28b9f0347348aedfb2bd6b9c945 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -113,7 +113,7 @@ RISCV_CORE("xt-c908v",        "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_"
                              "zvfh_sstc_svinval_svnapot_svpbmt__xtheadba_"
                              "xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_"
                              "xtheadfmemidx_xtheadmac_xtheadmemidx_"
-                             "xtheadmempair_xtheadsync_xtheadvdot",
+                             "xtheadmempair_xtheadsync",
                              "xt-c908")
 RISCV_CORE("xt-c910",         "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
                              "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
@@ -121,7 +121,7 @@ RISCV_CORE("xt-c910",         "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
                              "xtheadmemidx_xtheadmempair_xtheadsync",
                              "xt-c910")
 RISCV_CORE("xt-c910v2",       "rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_"
-                             "zicsr_zifencei _zihintntl_zihintpause_zihpm_"
+                             "zicsr_zifencei_zihintntl_zihintpause_zihpm_"
                              "zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
                              "zbs_sscofpmf_sstc_svinval_svnapot_svpbmt_"
                              "xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
@@ -135,13 +135,13 @@ RISCV_CORE("xt-c920",         "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"
                              "xtheadvector",
                              "xt-c910")
 RISCV_CORE("xt-c920v2",       "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_"
-                             "zicsr_zifencei _zihintntl_zihintpause_zihpm_"
+                             "zicsr_zifencei_zihintntl_zihintpause_zihpm_"
                              "zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_"
                              "zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_"
                              "svinval_svnapot_svpbmt_xtheadba_xtheadbb_"
                              "xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_"
                              "xtheadmac_xtheadmemidx_xtheadmempair_"
-                             "xtheadsync_xtheadvdot",
+                             "xtheadsync",
                               "xt-c920v2")
 
 RISCV_CORE("tt-ascalon-d8",   "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
index bb9e3109920a470d98e5fea7ca7be91997a08af5..c96d0b5865a4796a2438a626d9bd5a0b83b8f605 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c
@@ -4,7 +4,7 @@
 /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_
 zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_
 xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_
-xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */
+xtheadmemidx_xtheadmempair_xtheadsync */
 
 #if !((__riscv_xlen == 64)             \
       && !defined(__riscv_32e)         \
@@ -39,8 +39,7 @@ xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */
       && defined(__riscv_xtheadmac)            \
       && defined(__riscv_xtheadmemidx)         \
       && defined(__riscv_xtheadmempair)                \
-      && defined(__riscv_xtheadsync)           \
-      && defined (__riscv__xtheadvdot))
+      && defined(__riscv_xtheadsync))
 #error "unexpected arch"
 #endif
 

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
index 1f21d07f37ad37995b175f7559d8697c135372d1..806949e67a08cbe4fe06b765909cdae97bd2ed50 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { ! riscv_abi_e } } } */
 /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
 /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */
-/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */
+/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync */
 
 #if !((__riscv_xlen == 64)             \
       && !defined(__riscv_32e)         \
@@ -45,8 +45,7 @@
       && defined(__riscv_xtheadcmo)            \
       && defined(__riscv_xtheadcondmov)                \
       && defined(__riscv_xtheadfmemidx)                \
-      && defined(__riscv_xtheadsync)           \
-      && defined(__riscv_xtheadvdot))
+      && defined(__riscv_xtheadsync))
 #error "unexpected arch"
 #endif