arm64: dts: imx8mp pollux: add display overlays

imx8mp-phyboard-pollux had a display baked into its board dts file.
However this approach does not truly discribe the hardware and is not
suitable when using different displays.
Move display specific description into an overlay and add the successor
display for the phyboard-pollux as an additional overlay.

Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index f0ff9b4d18fe319e75c975ab3bd7470c1579ba9e..276172c1fd2cdde6acb3ffc88aa9f0ae9275a0e4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -226,7 +226,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
+imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
+       imx8mp-phyboard-pollux-etml1010g3dra.dtbo
+imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
+       imx8mp-phyboard-pollux-ph128800t006.dtbo
 imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso
new file mode 100644 (file)
index 0000000..7a7f27d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+/dts-v1/;
+/plugin/;
+
+&backlight_lvds1 {
+       brightness-levels = <0 8 16 32 64 128 255>;
+       default-brightness-level = <8>;
+       enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+       num-interpolated-steps = <2>;
+       pwms = <&pwm3 0 50000 0>;
+       status = "okay";
+};
+
+&lcdif2 {
+       status = "okay";
+};
+
+&lvds_bridge {
+       assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
+       assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+       /*
+        * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
+        * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
+        * engine can reach accurate pixel clock of exactly 72.4 MHz.
+        */
+       assigned-clock-rates = <0>, <506800000>;
+       status = "okay";
+};
+
+&panel_lvds1 {
+       compatible = "edt,etml1010g3dra";
+       status = "okay";
+};
+
+&pwm3 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso
new file mode 100644 (file)
index 0000000..a39f83b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+/dts-v1/;
+/plugin/;
+
+&backlight_lvds1 {
+       brightness-levels = <0 8 16 32 64 128 255>;
+       default-brightness-level = <8>;
+       enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+       num-interpolated-steps = <2>;
+       pwms = <&pwm3 0 66667 0>;
+       status = "okay";
+};
+
+&lcdif2 {
+       status = "okay";
+};
+
+&lvds_bridge {
+       assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
+       assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+       /*
+        * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
+        * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout
+        * engine can reach accurate pixel clock of exactly 66.5 MHz.
+        */
+       assigned-clock-rates = <0>, <465500000>;
+       status = "okay";
+};
+
+
+&panel_lvds1 {
+       compatible = "powertip,ph128800t006-zhc01";
+       status = "okay";
+};
+
+&pwm3 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index e97d1d7c629b7fc4b52931868e35cb2d98434513..9687b4ded8f4c98fe68bcbeedcb5ea03434e27a3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -7,7 +7,6 @@
 
 #include <dt-bindings/phy/phy-imx8-pcie.h>
 #include <dt-bindings/leds/leds-pca9532.h>
-#include <dt-bindings/pwm/pwm.h>
 #include <dt-bindings/thermal/thermal.h>
 #include "imx8mp-phycore-som.dtsi"
 
@@ -20,16 +19,12 @@
                stdout-path = &uart1;
        };
 
-       backlight_lvds: backlight {
+       backlight_lvds1: backlight1 {
                compatible = "pwm-backlight";
-               pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_lvds1>;
-               brightness-levels = <0 4 8 16 32 64 128 255>;
-               default-brightness-level = <11>;
-               enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
-               num-interpolated-steps = <2>;
+               pinctrl-names = "default";
                power-supply = <&reg_lvds1_reg_en>;
-               pwms = <&pwm3 0 50000 0>;
+               status = "disabled";
        };
 
        fan0: fan {
@@ -42,10 +37,11 @@
                #cooling-cells = <2>;
        };
 
-       panel1_lvds: panel-lvds {
-               compatible = "edt,etml1010g3dra";
-               backlight = <&backlight_lvds>;
+       panel_lvds1: panel-lvds1 {
+               /* compatible panel in overlay */
+               backlight = <&backlight_lvds1>;
                power-supply = <&reg_vcc_3v3_sw>;
+               status = "disabled";
 
                port {
                        panel1_in: endpoint {
@@ -231,32 +227,8 @@
        };
 };
 
-&lcdif2 {
-       status = "okay";
-};
-
-&lvds_bridge {
-       status = "okay";
-
-       ports {
-               port@2 {
-                       ldb_lvds_ch1: endpoint {
-                               remote-endpoint = <&panel1_in>;
-                       };
-               };
-       };
-};
-
-&media_blk_ctrl {
-       /*
-        * The LVDS panel on this device uses 72.4 MHz pixel clock,
-        * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
-        * serializer and LCDIFv3 scanout engine can reach accurate
-        * pixel clock of exactly 72.4 MHz.
-        */
-       assigned-clock-rates = <500000000>, <200000000>,
-                              <0>, <0>, <500000000>,
-                              <506800000>;
+&ldb_lvds_ch1 {
+       remote-endpoint = <&panel1_in>;
 };
 
 &snvs_pwrkey {
@@ -281,9 +253,8 @@
 };
 
 &pwm3 {
-       status = "okay";
-       pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm3>;
+       pinctrl-names = "default";
 };
 
 &rv3028 {