mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM base

The BAM command descriptor provides only 18 bits to specify the BAM
register offset. Additionally, in the BAM command descriptor, the BAM
register offset is supposed to be specified as "(NANDc base - BAM base)
+ reg_off". Since, the BAM controller expecting the value in the form of
"NANDc base - BAM base", so that added a new field 'bam_offset' in the NAND
properties structure and use it while preparing the command descriptor.

Previously, the driver was specifying the NANDc base address in the BAM
command descriptor.

Cc: stable@vger.kernel.org
Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor formation")
Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Acked-by: Mark Brown <broonie@kernel.org>
Tested-by: Gabor Juhos <j4g8y7@gmail.com> # on IPQ9574
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
index e0ed25b5afea9b289b767cd3d9c2d7572ed52008..4dc4d65e7d323e2843edecca8e3849a5090b775d 100644 (file)
--- a/drivers/mtd/nand/qpic_common.c
+++ b/drivers/mtd/nand/qpic_common.c
@@ -236,21 +236,21 @@ int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
        int i, ret;
        struct bam_cmd_element *bam_ce_buffer;
        struct bam_transaction *bam_txn = nandc->bam_txn;
+       u32 offset;
 
        bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
 
        /* fill the command desc */
        for (i = 0; i < size; i++) {
+               offset = nandc->props->bam_offset + reg_off + 4 * i;
                if (read)
                        bam_prep_ce(&bam_ce_buffer[i],
-                                   nandc_reg_phys(nandc, reg_off + 4 * i),
-                                   BAM_READ_COMMAND,
+                                   offset, BAM_READ_COMMAND,
                                    reg_buf_dma_addr(nandc,
                                                     (__le32 *)vaddr + i));
                else
                        bam_prep_ce_le32(&bam_ce_buffer[i],
-                                        nandc_reg_phys(nandc, reg_off + 4 * i),
-                                        BAM_WRITE_COMMAND,
+                                        offset, BAM_WRITE_COMMAND,
                                         *((__le32 *)vaddr + i));
        }
 

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 5eaa0be367cdb847d48dbed6f8326a75a5922347..ef2dd158ca34242c1b0ee49ee972a538a7c53409 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2360,6 +2360,7 @@ static const struct qcom_nandc_props ipq806x_nandc_props = {
        .supports_bam = false,
        .use_codeword_fixup = true,
        .dev_cmd_reg_start = 0x0,
+       .bam_offset = 0x30000,
 };
 
 static const struct qcom_nandc_props ipq4019_nandc_props = {
@@ -2367,6 +2368,7 @@ static const struct qcom_nandc_props ipq4019_nandc_props = {
        .supports_bam = true,
        .nandc_part_of_qpic = true,
        .dev_cmd_reg_start = 0x0,
+       .bam_offset = 0x30000,
 };
 
 static const struct qcom_nandc_props ipq8074_nandc_props = {
@@ -2374,6 +2376,7 @@ static const struct qcom_nandc_props ipq8074_nandc_props = {
        .supports_bam = true,
        .nandc_part_of_qpic = true,
        .dev_cmd_reg_start = 0x7000,
+       .bam_offset = 0x30000,
 };
 
 static const struct qcom_nandc_props sdx55_nandc_props = {
@@ -2382,6 +2385,7 @@ static const struct qcom_nandc_props sdx55_nandc_props = {
        .nandc_part_of_qpic = true,
        .qpic_version2 = true,
        .dev_cmd_reg_start = 0x7000,
+       .bam_offset = 0x30000,
 };
 
 /*

diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index 17eb67e19132612c4c1a84848fa6f7432b1130a8..d9fb602160c75b0ddb550e45b7ec6eb196eb420f 100644 (file)
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -1605,6 +1605,7 @@ static void qcom_spi_remove(struct platform_device *pdev)
 
 static const struct qcom_nandc_props ipq9574_snandc_props = {
        .dev_cmd_reg_start = 0x7000,
+       .bam_offset = 0x30000,
        .supports_bam = true,
 };
 

diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
index cd7172e6c1bbffeee0363a14044980a72ea17723..e8462deda6dbf61f99bbcb39e7cb12cdf66898fd 100644 (file)
--- a/include/linux/mtd/nand-qpic-common.h
+++ b/include/linux/mtd/nand-qpic-common.h
@@ -199,9 +199,6 @@
  */
 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
 
-/* Returns the NAND register physical address */
-#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
-
 /* Returns the dma address for reg read buffer */
 #define reg_buf_dma_addr(chip, vaddr) \
        ((chip)->reg_read_dma + \
@@ -454,6 +451,7 @@ struct qcom_nand_controller {
 struct qcom_nandc_props {
        u32 ecc_modes;
        u32 dev_cmd_reg_start;
+       u32 bam_offset;
        bool supports_bam;
        bool nandc_part_of_qpic;
        bool qpic_version2;