drm/xe/multi_queue: Add multi_queue_enable_mask to gt information

Add multi_queue_enable_mask field to the gt information structure
which is bitmask of all engine classes with multi queue support
enabled.

v2: Rename multi_queue_enable_mask to multi_queue_engine_class_mask
    (Matt Brost)

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251211010249.1647839-20-niranjana.vishwanathapura@intel.com

diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index 0f8a96a05a8ee8ab15a8e0d9b0b0b51e962788e9..4fa423a82bea86334c7e1a5c33fe7eaa3bfb4cef 100644 (file)
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data)
                           xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));
                drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,
                           gt->info.engine_mask);
+               drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id,
+                          gt->info.multi_queue_engine_class_mask);
        }
 
        return 0;

diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 0a728180b6fe5cdb9b0056fe6337adb688930e18..5318d92fd473f6677d612b8a60322b0ab4018b27 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -140,6 +140,11 @@ struct xe_gt {
                u64 engine_mask;
                /** @info.gmdid: raw GMD_ID value from hardware */
                u32 gmdid;
+               /**
+                * @multi_queue_engine_class_mask: Bitmask of engine classes with
+                * multi queue support enabled.
+                */
+               u16 multi_queue_engine_class_mask;
                /** @info.id: Unique ID of this GT within the PCI Device */
                u8 id;
                /** @info.has_indirect_ring_state: GT has indirect ring state support */

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index c8188a5b0f7611db00d80c4fda607958bf5f5e9d..16b3eb247439b5edf99cbaf5eb8a7c6d0f7f365b 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -764,6 +764,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
        gt->info.type = XE_GT_TYPE_MAIN;
        gt->info.id = tile->id * xe->info.max_gt_per_tile;
        gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
+       gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;
        gt->info.engine_mask = graphics_desc->hw_engine_mask;
 
        /*

diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index f19f35359696e5f7f88393ac4b63a0b79bea9208..b06c108e25e693e4e4cb0a0930f22bab4f845cf5 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -60,6 +60,7 @@ struct xe_device_desc {
 
 struct xe_graphics_desc {
        u64 hw_engine_mask;     /* hardware engines provided by graphics IP */
+       u16 multi_queue_engine_class_mask; /* bitmask of engine classes which support multi queue */
 
        u8 has_asid:1;
        u8 has_atomic_enable_pte_bit:1;