struct counter_count *count, u64 max)
{
struct intel_qep *qep = counter_priv(counter);
- int ret = 0;
/* Intel QEP ceiling configuration only supports 32-bit values */
if (max != (u32)max)
return -ERANGE;
- mutex_lock(&qep->lock);
- if (qep->enabled) {
- ret = -EBUSY;
- goto out;
- }
+ guard(mutex)(&qep->lock);
+
+ if (qep->enabled)
+ return -EBUSY;
pm_runtime_get_sync(qep->dev);
intel_qep_writel(qep, INTEL_QEPMAX, max);
pm_runtime_put(qep->dev);
-out:
- mutex_unlock(&qep->lock);
- return ret;
+ return 0;
}
static int intel_qep_enable_read(struct counter_device *counter,
u32 reg;
bool changed;
- mutex_lock(&qep->lock);
+ guard(mutex)(&qep->lock);
+
changed = val ^ qep->enabled;
if (!changed)
- goto out;
+ return 0;
pm_runtime_get_sync(qep->dev);
reg = intel_qep_readl(qep, INTEL_QEPCON);
pm_runtime_put(qep->dev);
qep->enabled = val;
-out:
- mutex_unlock(&qep->lock);
return 0;
}
struct intel_qep *qep = counter_priv(counter);
u32 reg;
bool enable;
- int ret = 0;
/*
* Spike filter length is (MAX_COUNT + 2) clock periods.
if (length > INTEL_QEPFLT_MAX_COUNT(length))
return -ERANGE;
- mutex_lock(&qep->lock);
- if (qep->enabled) {
- ret = -EBUSY;
- goto out;
- }
+ guard(mutex)(&qep->lock);
+
+ if (qep->enabled)
+ return -EBUSY;
pm_runtime_get_sync(qep->dev);
reg = intel_qep_readl(qep, INTEL_QEPCON);
intel_qep_writel(qep, INTEL_QEPCON, reg);
pm_runtime_put(qep->dev);
-out:
- mutex_unlock(&qep->lock);
- return ret;
+ return 0;
}
static int intel_qep_preset_enable_read(struct counter_device *counter,
{
struct intel_qep *qep = counter_priv(counter);
u32 reg;
- int ret = 0;
- mutex_lock(&qep->lock);
- if (qep->enabled) {
- ret = -EBUSY;
- goto out;
- }
+ guard(mutex)(&qep->lock);
+
+ if (qep->enabled)
+ return -EBUSY;
pm_runtime_get_sync(qep->dev);
reg = intel_qep_readl(qep, INTEL_QEPCON);
intel_qep_writel(qep, INTEL_QEPCON, reg);
pm_runtime_put(qep->dev);
-out:
- mutex_unlock(&qep->lock);
-
- return ret;
+ return 0;
}
static struct counter_comp intel_qep_count_ext[] = {