arm64: dts: renesas: r9a08g045: Add TSU node

Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.
The temperature reported by the TSU can only be read through channel 8 of
the ADC. Therefore, enable the ADC by default.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20250810122125.792966-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 16e6ac61441787790b70f35f81925ef2f3d24d85..11b7480b1a6828af0b13acac5eb61386f424e78e 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -233,7 +233,6 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #io-channel-cells = <1>;
-                       status = "disabled";
 
                        channel@0 {
                                reg = <0>;
@@ -272,6 +271,17 @@
                        };
                };
 
+               tsu: thermal@10059000 {
+                       compatible = "renesas,r9a08g045-tsu";
+                       reg = <0 0x10059000 0 0x1000>;
+                       clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
+                       resets = <&cpg R9A08G045_TSU_PRESETN>;
+                       power-domains = <&cpg>;
+                       #thermal-sensor-cells = <0>;
+                       io-channels = <&adc 8>;
+                       io-channel-names = "tsu";
+               };
+
                i3c: i3c@1005b000 {
                        compatible = "renesas,r9a08g045-i3c";
                        reg = <0 0x1005b000 0 0x1000>;
@@ -753,6 +763,43 @@
                                  "hyp-virt";
        };
 
+       thermal-zones {
+               cpu_thermal: cpu-thermal {
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&tsu>;
+                       sustainable-power = <423>;
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_alert0>;
+                                       cooling-device = <&cpu0 0 2>;
+                                       contribution = <1024>;
+                               };
+                       };
+
+                       trips {
+                               cpu_crit: cpu-critical {
+                                       temperature = <110000>;
+                                       hysteresis = <1000>;
+                                       type = "critical";
+                               };
+
+                               cpu_alert1: trip-point1 {
+                                       temperature = <90000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+
+                               cpu_alert0: trip-point0 {
+                                       temperature = <85000>;
+                                       hysteresis = <1000>;
+                                       type = "passive";
+                               };
+                       };
+               };
+       };
+
        vbattb_xtal: vbattb-xtal {
                compatible = "fixed-clock";
                #clock-cells = <0>;

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 39845faec89438c722c365efdc284df6929e0649..6f25ab6179829ed2901033f1c70149c4a7a629bf 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -84,10 +84,6 @@
        };
 };
 
-&adc {
-       status = "okay";
-};
-
 #if SW_CONFIG3 == SW_ON
 &eth0 {
        pinctrl-0 = <&eth0_pins>;