Set fpscr back to a known state after running generated code (64-bit mode).

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5615

diff --git a/coregrind/m_dispatch/dispatch-ppc64-linux.S b/coregrind/m_dispatch/dispatch-ppc64-linux.S
index f8f94deb4405c09a1ddac8798d06a89570febee5..28629145e5199aa874d58cf0a83618effdf4017e 100644 (file)
--- a/coregrind/m_dispatch/dispatch-ppc64-linux.S
+++ b/coregrind/m_dispatch/dispatch-ppc64-linux.S
@@ -432,19 +432,15 @@ VG_(run_innerloop__dispatch_profiled):
         /* We're leaving.  Check that nobody messed with
            VSCR or FPSCR. */
 
-       /* This check avoidance may be removable if stfiwx is
-       implemented. */
-#       if 0 //!defined(ENABLE_INNER)
-        /* Check FPSCR & 0xFF == 0 (lowest 8bits are controls)  */
-        mffs      4                       /* fpscr -> fpr */
-        li        5,144                   /* => 96(parent_sp) */
-        stfiwx    4,5,1                   /* fpr to stack */
-        lwzx      6,5,1                   /* load to gpr */
-        andi.     6,6,0xFF                /* mask wanted bits */
-        cmplwi    6,0x0                   /* cmp with zero */
-        bne       .invariant_violation    /* branch if not zero */
-#       endif
-
+       /* Set fpscr back to a known state, since vex-generated code
+          may have messed with fpscr[rm]. */
+        li      5,0
+        addi    1,1,-16
+        stw     5,0(1)
+        lfs     3,0(1)
+        addi    1,1,16
+        mtfsf   0xFF,3   /* fpscr = f3 */
+       
        /* Using r11 - value used again further on, so don't trash! */
        ld      11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
         ld      11,0(11)