cxl/port: Map Port RAS registers

In preparation for CXL VH (Virtual Host) topology protocol error handling,
add RAS capability registered mapping for all ports in a CXL VH topology.
This includes the RAS capabilities of Switch Upstream Ports, Switch
Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports
("downstream")

Update cxl_port_add_dport() to map the upstream RAS capability on first
'dport' attach.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Tested-by: Terry Bowman <terry.bowman@amd.com>
Link: https://patch.msgid.link/20260131000403.2135324-8-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index e90b7a91bf5de92d93da9d283df1106593bd0f88..b4be9c5715a60ef86fef5be564b9c5f5e22f2e6b 100644 (file)
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -166,6 +166,22 @@ void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
 }
 EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_rch_ras_setup, "CXL");
 
+void devm_cxl_port_ras_setup(struct cxl_port *port)
+{
+       struct cxl_register_map *map = &port->reg_map;
+
+       if (!map->component_map.ras.valid) {
+               dev_dbg(&port->dev, "RAS registers not found\n");
+               return;
+       }
+
+       map->host = &port->dev;
+       if (cxl_map_component_regs(map, &port->regs,
+                                  BIT(CXL_CM_CAP_CAP_ID_RAS)))
+               dev_dbg(&port->dev, "Failed to map RAS capability\n");
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL");
+
 void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
 {
        void __iomem *addr;

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 4479d632a687b33ecbe69d84b189c168dc138f56..626a37b72fc31241490f497965cc2895405c8215 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -607,6 +607,7 @@ struct cxl_dax_region {
  * @parent_dport: dport that points to this port in the parent
  * @decoder_ida: allocator for decoder ids
  * @reg_map: component and ras register mapping parameters
+ * @regs: mapped component registers
  * @nr_dports: number of entries in @dports
  * @hdm_end: track last allocated HDM decoder instance for allocation ordering
  * @commit_end: cursor to track highest committed decoder for commit ordering
@@ -628,6 +629,7 @@ struct cxl_port {
        struct cxl_dport *parent_dport;
        struct ida decoder_ida;
        struct cxl_register_map reg_map;
+       struct cxl_component_regs regs;
        int nr_dports;
        int hdm_end;
        int commit_end;

diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 65575371a35c9540cf8154d1bd61a4c6e891ee60..0cf64218aa16ec8ff4b85a07a89727b694c4de90 100644 (file)
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -82,6 +82,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev);
 pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
                                    pci_channel_state_t state);
 void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
+void devm_cxl_port_ras_setup(struct cxl_port *port);
 #else
 static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
 
@@ -94,6 +95,10 @@ static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
 static inline void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
 {
 }
+
+static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
+{
+}
 #endif
 
 #endif /* __CXL_PCI_H__ */

diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 929f7e259f0d3f29825b7a571a03ade4eee1c2ad..6ebd665fb347da9dca075337fd5cff6fe327d2fe 100644 (file)
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -192,6 +192,12 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
                rc = devm_cxl_switch_port_decoders_setup(port);
                if (rc)
                        return ERR_PTR(rc);
+
+               /*
+                * RAS setup is optional, either driver operation can continue
+                * on failure, or the device does not implement RAS registers.
+                */
+               devm_cxl_port_ras_setup(port);
        }
 
        dport = devm_cxl_add_dport_by_dev(port, dport_dev);