op = spinand->op_templates->read_cache;
- single = (op->cmd.buswidth == 1 && op->addr.buswidth == 1 && op->data.buswidth == 1);
- dtr = (op->cmd.dtr || op->addr.dtr || op->data.dtr);
- if (single && !dtr)
- io_mode = W35N01JW_VCR_IO_MODE_SINGLE_SDR;
- else if (!single && !dtr)
- io_mode = W35N01JW_VCR_IO_MODE_OCTAL_SDR;
- else if (!single && dtr)
- io_mode = W35N01JW_VCR_IO_MODE_OCTAL_DDR;
- else
- return -EINVAL;
-
- ret = w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode);
- if (ret)
- return ret;
-
dummy_cycles = ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dummy.dtr ? 2 : 1);
switch (dummy_cycles) {
case 8:
if (ret)
return ret;
+ single = (op->cmd.buswidth == 1 && op->addr.buswidth == 1 && op->data.buswidth == 1);
+ dtr = (op->cmd.dtr && op->addr.dtr && op->data.dtr);
+ if (single && !dtr)
+ io_mode = W35N01JW_VCR_IO_MODE_SINGLE_SDR;
+ else if (!single && !dtr)
+ io_mode = W35N01JW_VCR_IO_MODE_OCTAL_SDR;
+ else if (!single && dtr)
+ io_mode = W35N01JW_VCR_IO_MODE_OCTAL_DDR;
+ else
+ return -EINVAL;
+
+ ret = w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode);
+ if (ret)
+ return ret;
+
return 0;
}