aarch64: Add the missing tests for TLBI <operation> vmallws2e1

In the support for FEAT_TLBID feature patch, few <operation>
variants are added to the aarch64_sys_regs_tlbi table,
and that patch was missing the tests for following <operation>
variants, which are covered in this patch.

* VMALLWS2E1
* VMALLWS2E1IS
* VMALLWS2E1OS
* VMALLWS2E1NXS
* VMALLWS2E1ISNXS
* VMALLWS2E1OSNXS

diff --git a/gas/testsuite/gas/aarch64/tlbi-invalid-1.d b/gas/testsuite/gas/aarch64/tlbi-invalid-1.d
new file mode 100644 (file)
index 0000000..457bc91
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbi-invalid-1.d
@@ -0,0 +1,2 @@
+#name: Negative TLBI test with Rt !=  0b11111.
+#error_output: tlbi-invalid-1.l

diff --git a/gas/testsuite/gas/aarch64/tlbi-invalid-1.l b/gas/testsuite/gas/aarch64/tlbi-invalid-1.l
new file mode 100644 (file)
index 0000000..e9f7aa8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbi-invalid-1.l
@@ -0,0 +1,37 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Error: extraneous register at operand 2 -- `tlbi alle1,x0'
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Error: selected processor does not support system register name 'alle2os'
+.*: Error: extraneous register at operand 2 -- `tlbi alle2,x0'
+.*: Error: extraneous register at operand 2 -- `tlbi alle3is,x0'
+.*: Error: extraneous register at operand 2 -- `tlbi alle3,x0'
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: extraneous register at operand 2 -- `tlbi vmalle1,x0'
+.*: Error: selected processor does not support system register name 'vmalls12e1is'
+.*: Error: selected processor does not support system register name 'vmalls12e1os'
+.*: Error: extraneous register at operand 2 -- `tlbi vmalls12e1,x0'
+.*: Error: selected processor does not support system register name 'vmallws2e1is'
+.*: Error: selected processor does not support system register name 'vmallws2e1os'
+.*: Error: extraneous register at operand 2 -- `tlbi alle3os,x0'
+.*: Error: extraneous register at operand 2 -- `tlbi vmallws2e1,x0'
+.*: Error: selected processor does not support system register name 'alle1isnxs'
+.*: Error: selected processor does not support system register name 'alle1osnxs'
+.*: Error: extraneous register at operand 2 -- `tlbi alle1nxs,x0'
+.*: Error: selected processor does not support system register name 'alle2isnxs'
+.*: Error: selected processor does not support system register name 'alle2osnxs'
+.*: Error: extraneous register at operand 2 -- `tlbi alle2nxs,x0'
+.*: Error: extraneous register at operand 2 -- `tlbi alle3isnxs,x0'
+.*: Error: extraneous register at operand 2 -- `tlbi alle3nxs,x0'
+.*: Error: selected processor does not support system register name 'vmalle1osnxs'
+.*: Error: selected processor does not support system register name 'vmalle1osnxs'
+.*: Error: extraneous register at operand 2 -- `tlbi vmalle1nxs,x0'
+.*: Error: selected processor does not support system register name 'vmalls12e1isnxs'
+.*: Error: selected processor does not support system register name 'vmalls12e1osnxs'
+.*: Error: extraneous register at operand 2 -- `tlbi vmalls12e1nxs,x0'
+.*: Error: selected processor does not support system register name 'vmallws2e1isnxs'
+.*: Error: selected processor does not support system register name 'vmallws2e1osnxs'
+.*: Error: extraneous register at operand 2 -- `tlbi alle3osnxs,x0'
+.*: Error: extraneous register at operand 2 -- `tlbi vmallws2e1nxs,x0'

diff --git a/gas/testsuite/gas/aarch64/tlbi-invalid-1.s b/gas/testsuite/gas/aarch64/tlbi-invalid-1.s
new file mode 100644 (file)
index 0000000..b95d6dd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbi-invalid-1.s
@@ -0,0 +1,43 @@
+.arch armv8-a
+TLBI    alle1is, x0
+TLBI    alle1os, x0
+TLBI    alle1, x0
+TLBI    alle2is, x0
+TLBI    alle2os, x0
+TLBI    alle2, x0
+TLBI    alle3is, x0
+TLBI    alle3, x0
+TLBI    vmalle1os, x0
+TLBI    vmalle1os, x0
+TLBI    vmalle1, x0
+TLBI    vmalls12e1is, x0
+TLBI    vmalls12e1os, x0
+TLBI    vmalls12e1, x0
+TLBI    vmallws2e1is, x0
+TLBI    vmallws2e1os, x0
+
+.arch armv9.4-a
+TLBI    alle3os, x0
+TLBI    vmallws2e1, x0
+
+.arch armv8-a+xs
+TLBI    alle1isnxs, x0
+TLBI    alle1osnxs, x0
+TLBI    alle1nxs, x0
+TLBI    alle2isnxs, x0
+TLBI    alle2osnxs, x0
+TLBI    alle2nxs, x0
+TLBI    alle3isnxs, x0
+TLBI    alle3nxs, x0
+TLBI    vmalle1osnxs, x0
+TLBI    vmalle1osnxs, x0
+TLBI    vmalle1nxs, x0
+TLBI    vmalls12e1isnxs, x0
+TLBI    vmalls12e1osnxs, x0
+TLBI    vmalls12e1nxs, x0
+TLBI    vmallws2e1isnxs, x0
+TLBI    vmallws2e1osnxs, x0
+
+.arch armv9.4-a+xs
+TLBI    alle3osnxs, x0
+TLBI    vmallws2e1nxs, x0

diff --git a/gas/testsuite/gas/aarch64/tlbi-vmallws2e1.d b/gas/testsuite/gas/aarch64/tlbi-vmallws2e1.d
new file mode 100644 (file)
index 0000000..f9d903e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbi-vmallws2e1.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:    d50c867f        tlbi    vmallws2e1
+.*:    d50c825f        tlbi    vmallws2e1is
+.*:    d50c855f        tlbi    vmallws2e1os
+.*:    d50c967f        tlbi    vmallws2e1nxs
+.*:    d50c925f        tlbi    vmallws2e1isnxs
+.*:    d50c955f        tlbi    vmallws2e1osnxs
+.*:    d50c8240        tlbi    vmallws2e1is, x0
+.*:    d50c8540        tlbi    vmallws2e1os, x0
+.*:    d50c9240        tlbi    vmallws2e1isnxs, x0
+.*:    d50c9540        tlbi    vmallws2e1osnxs, x0

diff --git a/gas/testsuite/gas/aarch64/tlbi-vmallws2e1.s b/gas/testsuite/gas/aarch64/tlbi-vmallws2e1.s
new file mode 100644 (file)
index 0000000..8ecceb5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbi-vmallws2e1.s
@@ -0,0 +1,17 @@
+       .arch armv8.4-a
+       TLBI VMALLWS2E1
+       TLBI VMALLWS2E1IS
+       TLBI VMALLWS2E1OS
+
+       .arch armv8.4-a+xs
+       TLBI VMALLWS2E1NXS
+       TLBI VMALLWS2E1ISNXS
+       TLBI VMALLWS2E1OSNXS
+
+       .arch armv8.4-a+tlbid
+       TLBI VMALLWS2E1IS, x0
+       TLBI VMALLWS2E1OS, x0
+
+       .arch armv8.4-a+tlbid+xs
+       TLBI VMALLWS2E1ISNXS, x0
+       TLBI VMALLWS2E1OSNXS, x0