arm64: dts: qcom: talos: Add QSPI support

The Talos (QCS615) platform includes a QSPI controller used for accessing
external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
the QSPI controller node to enable support for this hardware.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260429-spi-nor-v5-4-993016c9711e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index ff5afbfce2a4744777829a1938754f02a5f6cb5c..8c7ea369a332fe5389b61be85331e9fd9965d796 100644 (file)
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -531,6 +531,25 @@
 
        };
 
+       qspi_opp_table: opp-table-qspi {
+               compatible = "operating-points-v2";
+
+               opp-60000000 {
+                       opp-hz = /bits/ 64 <60000000>;
+                       required-opps = <&rpmhpd_opp_low_svs>;
+               };
+
+               opp-133250000 {
+                       opp-hz = /bits/ 64 <133250000>;
+                       required-opps = <&rpmhpd_opp_svs>;
+               };
+
+               opp-266500000 {
+                       opp-hz = /bits/ 64 <266500000>;
+                       required-opps = <&rpmhpd_opp_nom>;
+               };
+       };
+
        qup_opp_table: opp-table-qup {
                compatible = "operating-points-v2";
 
@@ -1610,6 +1629,34 @@
                                bias-pull-up;
                        };
 
+                       qspi_cs0: qspi-cs0-state {
+                               pins = "gpio44";
+                               function = "qspi";
+                               bias-disable;
+                               drive-strength = <6>;
+                       };
+
+                       qspi_data0123: qspi-data0123-state {
+                               pins = "gpio45", "gpio46", "gpio47", "gpio49";
+                               function = "qspi";
+                               bias-pull-down;
+                               drive-strength = <6>;
+                       };
+
+                       qspi_clk: qspi-clk-state {
+                               pins = "gpio48";
+                               function = "qspi";
+                               bias-pull-down;
+                               drive-strength = <6>;
+                       };
+
+                       qspi_cs1: qspi-cs1-state {
+                               pins = "gpio50";
+                               function = "qspi";
+                               bias-pull-down;
+                               drive-strength = <6>;
+                       };
+
                        qup_i2c1_data_clk: qup-i2c1-data-clk-state {
                                pins = "gpio4", "gpio5";
                                function = "qup0";
@@ -3896,6 +3943,39 @@
                        };
                };
 
+               qspi: spi@88df000 {
+                       compatible = "qcom,qcs615-qspi",
+                                    "qcom,qspi-v1";
+                       reg = <0x0 0x088df000 0x0 0x1000>;
+
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>;
+
+                       clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+                                <&gcc GCC_QSPI_CORE_CLK>;
+                       clock-names = "iface",
+                                     "core";
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "qspi-config",
+                                            "qspi-memory";
+
+                       power-domains = <&rpmhpd RPMHPD_CX>;
+                       operating-points-v2 = <&qspi_opp_table>;
+
+                       iommus = <&apps_smmu 0x160 0x0>;
+
+                       pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>;
+                       pinctrl-names = "default";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
                dc_noc: interconnect@9160000 {
                        reg = <0x0 0x09160000 0x0 0x3200>;
                        compatible = "qcom,qcs615-dc-noc";