drm/xe: Consolidate workaround entries for Wa_18041344222

Wa_18041344222 applies to all graphics versions from 20.01 through 30.00
(inclusive).  Consolidate the RTP entries into a single range-based
entry.

v2:
 - Drop the FUNC(xe_rtp_match_not_sriov_vf) to align with commit
   a800b95c2498 ("drm/xe/xe2hpg: Remove SRIOV VF check for
   Wa_18041344222") and commit 0ffe9dcf260b ("drm/xe/xe3: Remove SRIOV
   VF check for Wa_18041344222") which just landed.  (Shuicheng)

Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260223-forupstream-wa_cleanup-v3-1-7f201eb2f172@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 50f5d3381b4cdbf11760b350b9ba151ab828a717..d1a8c375ba0314046ca788caf6e15bcdcd236d53 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -385,6 +385,12 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
        },
+       { XE_RTP_NAME("18041344222"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000),
+                      FUNC(xe_rtp_match_first_render_or_compute),
+                      FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
+         XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
+       },
 
        /* TGL */
 
@@ -531,12 +537,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
        },
-       { XE_RTP_NAME("18041344222"),
-         XE_RTP_RULES(GRAPHICS_VERSION(2004),
-                      FUNC(xe_rtp_match_first_render_or_compute),
-                      FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
-         XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
-       },
 
        /* Xe2_HPG */
 
@@ -555,12 +555,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
        },
-       { XE_RTP_NAME("18041344222"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
-                      FUNC(xe_rtp_match_first_render_or_compute),
-                      FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
-         XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
-       },
 
        /* Xe3_LPG */
 
@@ -586,12 +580,6 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
                             XE_RTP_ACTION_FLAG(ENGINE_BASE)))
        },
-       { XE_RTP_NAME("18041344222"),
-         XE_RTP_RULES(GRAPHICS_VERSION(3000),
-                      FUNC(xe_rtp_match_first_render_or_compute),
-                      FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
-         XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
-       },
 
        /* Xe3p_LPG*/