drm/i915/lt_phy: Readout lane count

Readout lane count back from HW. Reuse existing function
for Cx0 for LT PHY case with minor modification to add
lanes as function parameters.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-20-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6a471c021c0e6d0c013cc4db314e521ad22b894c..7e59409bbf0134e909dcfae8de48133e81c0e38a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2180,7 +2180,7 @@ static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
        return 0;
 }
 
-static int readout_enabled_lane_count(struct intel_encoder *encoder)
+int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1)
 {
        struct intel_display *display = to_intel_display(encoder);
        u8 enabled_tx_lane_count = 0;
@@ -2212,7 +2212,7 @@ static int readout_enabled_lane_count(struct intel_encoder *encoder)
                max_tx_lane_count = round_up(max_tx_lane_count, 2);
 
        for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
-               u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+               u8 phy_lane_mask = tx_lane < 2 ? lane0 : lane1;
                int tx = tx_lane % 2 + 1;
                u8 val;
 
@@ -2252,7 +2252,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
         */
        intel_c10_msgbus_access_begin(encoder, lane);
 
-       cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+       cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,
+                                                           INTEL_CX0_LANE1);
 
        for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
                pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
@@ -2707,7 +2708,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 
        wakeref = intel_cx0_phy_transaction_begin(encoder);
 
-       cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+       cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,
+                                                           INTEL_CX0_LANE1);
 
        /* 1. Read VDR params and current context selection */
        intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 1d4480b8bf3948f0cb4f093ab42bca52b3983535..1428e7a5a318bcf2722050c2ef5ea726ba787d9f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -28,6 +28,7 @@ struct intel_hdmi;
 void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
                                         int lane);
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
+int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
                          struct intel_dpll *pll,
                          const struct intel_dpll_hw_state *dpll_hw_state);

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 62719082efda1f3a542df3f9ce051b10c7d5916c..e9fce044b99dafb28ddfc63e36d65ed2066ec9cd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2232,6 +2232,8 @@ bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
        lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
        wakeref = intel_lt_phy_transaction_begin(encoder);
 
+       pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_LT_PHY_LANE0,
+                                                        INTEL_LT_PHY_LANE1);
        pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
        pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
        pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);