drm/amdgpu: Missing multi-XCC support in MES

In a multi-XCC GPU, pass the master XCC's ID to amdgpu_mes_suspend,
amdgpu_mes_resume, and detect_and_reset_hung_queues so the command will be
sent to the matching master MES when the compute partition mode is not
SPX.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index bdf2561b5404e0c4eca4a3f508e6d3d33d766413..c845bd39ddbf3a84aaa38c58d3dfcad7cdaba9f5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -301,7 +301,7 @@ void amdgpu_mes_fini(struct amdgpu_device *adev)
        mutex_destroy(&adev->mes.mutex_hidden);
 }
 
-int amdgpu_mes_suspend(struct amdgpu_device *adev)
+int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id)
 {
        struct mes_suspend_gang_input input;
        int r;
@@ -311,6 +311,7 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev)
 
        memset(&input, 0x0, sizeof(struct mes_suspend_gang_input));
        input.suspend_all_gangs = 1;
+       input.xcc_id = xcc_id;
 
        /*
         * Avoid taking any other locks under MES lock to avoid circular
@@ -325,7 +326,7 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev)
        return r;
 }
 
-int amdgpu_mes_resume(struct amdgpu_device *adev)
+int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id)
 {
        struct mes_resume_gang_input input;
        int r;
@@ -335,6 +336,7 @@ int amdgpu_mes_resume(struct amdgpu_device *adev)
 
        memset(&input, 0x0, sizeof(struct mes_resume_gang_input));
        input.resume_all_gangs = 1;
+       input.xcc_id = xcc_id;
 
        /*
         * Avoid taking any other locks under MES lock to avoid circular
@@ -463,6 +465,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
                adev->mes.hung_queue_db_array_size * sizeof(u32));
        input.queue_type = queue_type;
        input.detect_only = detect_only;
+       input.xcc_id = xcc_id;
 
        r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes,
                                                          &input);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index cafc5caae82241e4fd6c0256efb8bddb950ce0af..282941c0b51913836df288cdca2e714206fc4d4a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -325,8 +325,9 @@ struct mes_reset_queue_input {
 };
 
 struct mes_detect_and_reset_queue_input {
-       uint32_t                           queue_type;
-       bool                               detect_only;
+       u32     queue_type;
+       bool            detect_only;
+       u32     xcc_id;
 };
 
 struct mes_inv_tlbs_pasid_input {
@@ -442,8 +443,8 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
 int amdgpu_mes_init(struct amdgpu_device *adev);
 void amdgpu_mes_fini(struct amdgpu_device *adev);
 
-int amdgpu_mes_suspend(struct amdgpu_device *adev);
-int amdgpu_mes_resume(struct amdgpu_device *adev);
+int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id);
+int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id);
 
 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
                                struct amdgpu_ring *ring, uint32_t xcc_id);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 1ffbb5450f3a54fed93ad257d26fe7be47cfc75f..2c6f1e25ca145ee300f11cfcec2797066ddf3538 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5224,7 +5224,7 @@ static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block)
        /**
         * GFX soft reset will impact MES, need resume MES when do GFX soft reset
         */
-       return amdgpu_mes_resume(adev);
+       return amdgpu_mes_resume(adev, 0);
 }
 
 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index 2fc39a6938f6db668c61a5c70036e75363374198..a171fc9c89748b875dc8aa1036490825469741e9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
@@ -266,7 +266,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev,
 
        if (found_hung_queue) {
                /* Resume scheduling after hang recovery */
-               r = amdgpu_mes_resume(adev);
+               r = amdgpu_mes_resume(adev, input.xcc_id);
        }
 
        return r;

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index ab3b2e7be9bd045f5639e73d6da1531414e96802..8404440b8cb6487f07d19992c15e3001b946651e 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -367,7 +367,7 @@ static int suspend_all_queues_mes(struct device_queue_manager *dqm)
        if (!down_read_trylock(&adev->reset_domain->sem))
                return -EIO;
 
-       r = amdgpu_mes_suspend(adev);
+       r = amdgpu_mes_suspend(adev, ffs(dqm->dev->xcc_mask) - 1);
        up_read(&adev->reset_domain->sem);
 
        if (r) {
@@ -387,7 +387,7 @@ static int resume_all_queues_mes(struct device_queue_manager *dqm)
        if (!down_read_trylock(&adev->reset_domain->sem))
                return -EIO;
 
-       r = amdgpu_mes_resume(adev);
+       r = amdgpu_mes_resume(adev, ffs(dqm->dev->xcc_mask) - 1);
        up_read(&adev->reset_domain->sem);
 
        if (r) {