sunxi: clock: H6: unify PLL control bit definitions

The Allwinner PLLs share most of their control bits, they differ mostly
in the factors and dividers.

Drop the PLL specific definition of those common bits, and use one
shared macro, for all PLLs.

This requires changing the users in the SPL clock and DRAM code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 575dff688046aceea5954bbc36c118f9eb5bc789..37a620c9866e9a348f1312a173e2b417da12edf0 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -31,29 +31,23 @@
 #define CCU_H6_UART_GATE_RESET         0x90c
 #define CCU_H6_I2C_GATE_RESET          0x91c
 
-/* pll1 bit field */
-#define CCM_PLL1_CTRL_EN               BIT(31)
-#define CCM_PLL1_LDO_EN                        BIT(30)
-#define CCM_PLL1_LOCK_EN               BIT(29)
-#define CCM_PLL1_LOCK                  BIT(28)
-#define CCM_PLL1_OUT_EN                        BIT(27)
+/* PLL bit fields */
+#define CCM_PLL_CTRL_EN                        BIT(31)
+#define CCM_PLL_LDO_EN                 BIT(30)
+#define CCM_PLL_LOCK_EN                        BIT(29)
+#define CCM_PLL_LOCK                   BIT(28)
+#define CCM_PLL_OUT_EN                 BIT(27)
+#define CCM_PLL1_UPDATE                        BIT(26)
 #define CCM_PLL1_CLOCK_TIME_2          (2 << 24)
 #define CCM_PLL1_CTRL_P(p)             ((p) << 16)
 #define CCM_PLL1_CTRL_N(n)             (((n) - 1) << 8)
 
 /* pll5 bit field */
-#define CCM_PLL5_CTRL_EN               BIT(31)
-#define CCM_PLL5_LOCK_EN               BIT(29)
-#define CCM_PLL5_LOCK                  BIT(28)
-#define CCM_PLL5_OUT_EN                        BIT(27)
 #define CCM_PLL5_CTRL_N(n)             (((n) - 1) << 8)
 #define CCM_PLL5_CTRL_DIV1(div1)       ((div1) << 0)
 #define CCM_PLL5_CTRL_DIV2(div0)       ((div0) << 1)
 
 /* pll6 bit field */
-#define CCM_PLL6_CTRL_EN               BIT(31)
-#define CCM_PLL6_LOCK_EN               BIT(29)
-#define CCM_PLL6_LOCK                  BIT(28)
 #define CCM_PLL6_CTRL_P0_SHIFT         16
 #define CCM_PLL6_CTRL_P0_MASK          (0x7 << CCM_PLL6_CTRL_P0_SHIFT)
 #define CCM_PLL6_CTRL_N_SHIFT          8

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 3f375a519655d4626d6fc32b033847618aafaf12..2f2fd5df93d44c9ebd3667852443795e16bcbb5c 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
@@ -31,7 +33,7 @@ void clock_init_safe(void)
        clock_set_pll1(408000000);
 
        writel(CCM_PLL6_DEFAULT, ccm + CCU_H6_PLL6_CFG);
-       while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL6_LOCK))
+       while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL_LOCK))
                ;
 
        clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG,
@@ -85,15 +87,16 @@ void clock_set_pll1(unsigned int clk)
        writel(val, ccm + CCU_H6_CPU_AXI_CFG);
 
        /* clk = 24*n/p, p is ignored if clock is >288MHz */
-       val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
+       val = CCM_PLL_CTRL_EN | CCM_PLL_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
        val |= CCM_PLL1_CTRL_N(clk / 24000000);
        if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
            IS_ENABLED(CONFIG_MACH_SUN50I_A133))
-              val |= CCM_PLL1_OUT_EN;
+               val |= CCM_PLL_OUT_EN;
        if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
-              val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
+               val |= CCM_PLL_OUT_EN | CCM_PLL_LDO_EN;
        writel(val, ccm + CCU_H6_PLL1_CFG);
-       while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL1_LOCK)) {}
+       while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL_LOCK))
+               ;
 
        /* Switch CPU to PLL1 */
        val = readl(ccm + CCU_H6_CPU_AXI_CFG);

diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c
index a0fca3738f46454c50a9cfc722bc28eceac3c59f..3a231141168e267601c2901df4a460b29a2dcc13 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_a133.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c
@@ -78,19 +78,19 @@ static void mctl_clk_init(u32 clk)
        clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET);
        clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT));
        clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT));
-       clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+       clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN);
        clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
        udelay(5);
 
        /* Set up PLL5 clock, used for DRAM */
        clrsetbits_le32(ccm + CCU_H6_PLL5_CFG, 0xff03,
-                       CCM_PLL5_CTRL_N((clk * 2) / 24) | CCM_PLL5_CTRL_EN);
+                       CCM_PLL5_CTRL_N((clk * 2) / 24) | CCM_PLL_CTRL_EN);
        setbits_le32(ccm + CCU_H6_PLL5_CFG, BIT(24));
        clrsetbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3,
-                       CCM_PLL5_LOCK_EN | CCM_PLL5_CTRL_EN | BIT(30));
-       clrbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3 | BIT(30));
+                       CCM_PLL_LOCK_EN | CCM_PLL_CTRL_EN | CCM_PLL_LDO_EN);
+       clrbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3 | CCM_PLL_LDO_EN);
        mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
-                             CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+                             CCM_PLL_LOCK, CCM_PLL_LOCK);
 
        /* Enable DRAM clock and gate*/
        clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, BIT(24) | BIT(25));

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 84fd64a2bfc32c7c6ed6d6e7d24587d7cfbfda58..ea26e6dd3272be565d5272164447f8ab9ec4f62f 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -167,16 +167,16 @@ static void mctl_sys_init(u32 clk_rate)
        clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0));
        udelay(5);
        writel(0, ccm + CCU_H6_DRAM_GATE_RESET);
-       clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+       clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN);
        clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
 
        udelay(5);
 
        /* Set PLL5 rate to doubled DRAM clock rate */
-       writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
+       writel(CCM_PLL_CTRL_EN | CCM_PLL_LOCK_EN |
               CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG);
        mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
-                             CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+                             CCM_PLL_LOCK, CCM_PLL_LOCK);
 
        /* Configure DRAM mod clock */
        writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG);

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 5a59f82d1eff0a4d6aeb92b49c48f9b6b3523703..877181016f385e1fba766affe9e73c696b9027e0 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -106,16 +106,16 @@ static void mctl_sys_init(u32 clk_rate)
        clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT));
        udelay(5);
        clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT));
-       clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN);
+       clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN);
        clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET);
 
        udelay(5);
 
        /* Set PLL5 rate to doubled DRAM clock rate */
-       writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN |
+       writel(CCM_PLL_CTRL_EN | CCM_PLL_LOCK_EN | CCM_PLL_OUT_EN |
               CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG);
        mctl_await_completion(ccm + CCU_H6_PLL5_CFG,
-                             CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+                             CCM_PLL_LOCK, CCM_PLL_LOCK);
 
        /* Configure DRAM mod clock */
        writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG);