perf amd ibs: Suppress bogus TlbRefillLat and DCPhysAd on Zen4+

On Zen4 (and future) CPUs, IBS_OP_DATA3[TlbRefillLat] is valid only if
IBS_OP_DATA3[DcPhyAddrValid] is set. Similarly, IBS_DC_PHYSADDR is valid
if IBS_OP_DATA3[DcLinAddrValid] is _also_ set. Add these checks while
decoding IBS MSRs.

When IBS is triggered by an unprivileged user, the kernel now zeroes
PhysAddr before storing raw IBS register values in the perf sample. The
perf tool, however, still outputs these zero physical addresses, which
serves no purpose. So avoid printing zero physical addresses.

Instead of explicit family/model checks use the !zen4_ibs_extensions as
a proxy flag to cover Zen 3 and earlier revisions.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Dapeng Mi <dapeng1.mi@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Manali Shukla <manali.shukla@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Santosh Shukla <santosh.shukla@amd.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/util/amd-sample-raw.c b/tools/perf/util/amd-sample-raw.c
index b084dee76b1a758ed66ea0d3321916c86dfc57fd..385308c55f347e28cfa2da49cf751f591ca52fd0 100644 (file)
--- a/tools/perf/util/amd-sample-raw.c
+++ b/tools/perf/util/amd-sample-raw.c
@@ -172,6 +172,7 @@ static void pr_ibs_op_data3(union ibs_op_data3 reg)
        char dc_l1_l2tlb_miss_str[sizeof(" DcL1TlbMiss _ DcL2TlbMiss _")] = "";
        char dc_l1tlb_hit_str[sizeof(" DcL1TlbHit2M _ DcL1TlbHit1G _")] = "";
        char op_mem_width_str[sizeof(" OpMemWidth _____ bytes")] = "";
+       char tlb_refill_lat_str[sizeof(" TlbRefillLat _____")] = "";
        char dc_l2tlb_hit_2m_str[sizeof(" DcL2TlbHit2M _")] = "";
        char dc_l2tlb_hit_1g_str[sizeof(" DcL2TlbHit1G _")] = "";
        char dc_page_size_str[sizeof(" DcPageSize ____")] = "";
@@ -214,17 +215,23 @@ static void pr_ibs_op_data3(union ibs_op_data3 reg)
                         " DcL2TlbHit1G %d", reg.dc_l2_tlb_hit_1g);
        }
 
+       /* Use !zen4_ibs_extensions as a proxy for Zen3 and earlier */
+       if (!zen4_ibs_extensions || reg.dc_phy_addr_valid) {
+               snprintf(tlb_refill_lat_str, sizeof(tlb_refill_lat_str),
+                        " TlbRefillLat %5d", reg.tlb_refill_lat);
+       }
+
        printf("ibs_op_data3:\t%016llx LdOp %d StOp %d%s%s%s DcMiss %d DcMisAcc %d "
                "DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d "
                "DcLinAddrValid %d DcPhyAddrValid %d%s%s SwPf %d%s%s "
-               "DcMissLat %5d TlbRefillLat %5d\n",
+               "DcMissLat %5d%s\n",
                reg.val, reg.ld_op, reg.st_op, dc_l1_l2tlb_miss_str,
                dtlb_pgsize_cap ? dc_page_size_str : dc_l1tlb_hit_str,
                dc_l2tlb_hit_2m_str, reg.dc_miss, reg.dc_mis_acc, reg.dc_wc_mem_acc,
                reg.dc_uc_mem_acc, reg.dc_locked_op, reg.dc_miss_no_mab_alloc,
                reg.dc_lin_addr_valid, reg.dc_phy_addr_valid, dc_l2tlb_hit_1g_str,
                l2_miss_str, reg.sw_pf, op_mem_width_str, op_dc_miss_open_mem_reqs_str,
-               reg.dc_miss_lat, reg.tlb_refill_lat);
+               reg.dc_miss_lat, tlb_refill_lat_str);
 }
 
 /*
@@ -253,8 +260,12 @@ static void amd_dump_ibs_op(struct perf_sample *sample)
        pr_ibs_op_data3(*op_data3);
        if (op_data3->dc_lin_addr_valid)
                printf("IbsDCLinAd:\t%016llx\n", *(rip + 4));
-       if (op_data3->dc_phy_addr_valid)
+
+       /* Use !zen4_ibs_extensions as a proxy for Zen3 and earlier */
+       if (op_data3->dc_phy_addr_valid && *(rip + 5) &&
+           (!zen4_ibs_extensions || op_data3->dc_lin_addr_valid)) {
                printf("IbsDCPhysAd:\t%016llx\n", *(rip + 5));
+       }
        if (op_data->op_brn_ret && *(rip + 6))
                printf("IbsBrTarget:\t%016llx\n", *(rip + 6));
 }